| [摘要] | ||
| 在製程技術不斷精進的今日，元件線寬已到達了深次微米的領域， | ||
| 在0.35 um，0.25 um甚至到0.18 um的製程下，CMOS積體電路因靜電放電 | ||
| 而損傷的問題越來越嚴重。一方面為了解靜電放電防護元件之物理特性， | ||
| 一方面更為能在晶片製作完成之初，能先了解產品之靜電放電的承受能力 | ||
| ，因此在先進國家中，傳輸線觸波產生器已被架設用來量測元件之二次崩 | ||
| 潰點，並和靜電放電標準測試模式互相參照比較，由理論的探討中，可得 | ||
| 知其關係為正比之線性關係。在本論文中，我們架設了台灣本土的第一套 | ||
| 傳輸線觸波產生器，並用來量測及研究靜電放電防護元件的二次崩潰特性 | ||
| 。藉由對元件二次崩潰特性的了解，我們提出了基體觸發的技術，用來提 | ||
| 昇深次微米製程技術下，靜電放電防護電路的防護能力及效果。由實驗的 | ||
| 分析中可知，利用基體的偏壓可提供靜電放電保護電路更有效的防護能力 | ||
| 。在本論文中，即利用此種基體觸發技術設計出四種不同元件結構的保護 | ||
| 電路，並利用四邊形元件的佈局設計方式來實現這四種靜電放電防護元件 | ||
| 。在此四種基體觸發靜電放電防護電路中，分別利用了水平寄生雙載子電 | ||
| 晶體及垂直寄生雙載子電晶體，以及以一般金氧半場效電晶體的結構與隔 | ||
| 絕氧化層式電晶體的結構方式來設計，而設計出相當節省面積的靜電放電 | ||
| 保護元件。這四種基體觸發靜電放電防護電路已完成晶片製作於－0.6um | ||
| CMOS製程中，實驗結果顯示，以雙重雙載子電晶體設計的保護電路在單位 | ||
| 佈局面積下，其對靜電放電的保護能力比以傳統利用NMOS元件的保護電路 | ||
| 高出兩倍。本論文之研究成果，即將發表在IEEE的國際學術研討會上，並 | ||
| 已進行專利的申請。
[摘要] |
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| In the advanced deep-submicron CMOS technology, it is more | ||
| difficult to prevent damages from the ESD (Electrostatic | ||
| Discharge) stresses. To understand the physical characteristics | ||
| and ESD robustness of protection devices in the wafer level, a | ||
| transmission line pulsing generator (TLPG) system had been set | ||
| up in several advanced companies to measure the secondary | ||
| breakdown characteristics of the protection devices. The | ||
| relationship between the secondary breakdown current and the ESD | ||
| level of the ESD protection devices is a linear function. In | ||
| this thesis, the first transmission line pulsing generator | ||
| system in Taiwan has been set up and used to measure and analyze | ||
| the secondary breakdown characteristics of the ESD protection | ||
| devices. Based on the understanding on the secondary breakdown | ||
| characteristics of the protection devices, a substrate- | ||
| triggering technique has been developed in this thesis and used | ||
| to improve the protection efficiency of the ESD protection | ||
| circuits in the deep-submicron CMOS technologies.From the | ||
| experimental measurement results, the substrate bias can | ||
| effectively increase the secondary-breakdown current of the ESD | ||
| protection devices. Through suitable circuit design to apply the | ||
| substrate bias, the substrate-triggering technique has been | ||
| proposed in this thesis to improve ESD robustness of the ESD | ||
| protection circuits for deep-submicron CMOS IC's. In this | ||
| thesis, four new device structures by using the proposed | ||
| substrate-triggering technique are designed and investigated for | ||
| power-rail ESD clamp circuits. The multiple-cell square-type | ||
| layout concept is also applied to realize the four ESD | ||
| protection devices to improve their uniform turn-on behaviors. A | ||
| test chip to verify the efficiency of ESD clamp circuits has | ||
| been designed and fabricated in a 0.6-mm CMOS process. The | ||
| experimental results have confirmed that the double-BJT | ||
| structure with the substrate-triggering technique can provide | ||
| 200% higher ESD robustness in per unit layout area than that of | ||
| the traditional design with the NMOS device.The design and | ||
| experimental results will be presented in the IEEE International | ||
| ASIC Conference and submitted for U.S.A. and R.O.C. patents. |