[摘要]

在深次微米低電壓金氧半積體電路之輸出與輸入級設計中有兩個主要的考慮，其一是靜電

放電保護能力，因閘級氧化層越來越薄，對靜電放電的承受能力也相對減低，所以積體電

路產品之靜電放電保護能力已成為一重要的研究課題；另一方面則為雜訊之抑制，因金氧

半積體電路高速運算的應用，且操作電壓也日趨降低，此時輸出入訊號的高低電壓準位日

趨接近，造成積體電路對雜訊的容忍度亦大為降低，所以在設計積體電路的輸出驅動器時

，必須要有效地控制同步切換所造成之雜訊。因此，本論文可分為兩個主要部分，一是對

互補式金氧半（CMOS）積體電路的靜電放電保護技術之研究，另一是有關低同步切換雜訊

輸出驅動級之設計。　本論文的第一部分提出了四種新型的靜電放電保護電路: (1) 第一

是利用完全互補式低電壓觸發矽控整流器來設計靜電放電防護電路，結合短通道金氧半元

件及矽控整流器結構，在輸入或輸出端到電源端（VDD）及接地端（VSS）提供有效且直接

的靜電放電排放路徑，此低電壓觸發矽控整流器具有短通道金氧半元件之低觸發電壓及矽

控整流器之大電流旁通能力。此設計提供四條有效的放電路徑以因應四種不同的靜電放電

測試組合，如此積體電路中的內部電路可獲得有效的保護。實驗結果證明與傳統保護電路

相比，此電路可在最小的佈局面積下提供最大的靜電放電保護能力，且在高溫（150℃）下

亦可安全地工作。(2) 第二是利用電容耦合技術來設計靜電放電保護電路，電容耦合技術

被用來降低金氧半元件之觸發電壓，且能促進靜電放電電流的均勻分佈以提昇靜電放電防

護能力，此耦合電容可放置於打線墊片之下，不會增加額外之佈局面積。設計公式用以計

算靜電放電保護電路的電容耦合效率已被詳細推導出來。實驗結果證明此電路可用來

保護在深次微米低電壓製程技術下的金氧半積體電路輸入級之閘級薄氧化層。(3) 第三是

電容耦合低電壓觸發矽控整流器之設計，本設計同時結合電容耦合技術與互補式低電壓觸

發矽控整流器而成之靜電放電保護電路，能夠更有效地保護深次微米金氧半積體電路而不

需要佔用大的佈局面積。應用電容耦合技術可以更加降低該低電壓觸發矽控整流器的觸發

電壓，如此積體電路之內部電路可獲得更為有效的保護，實驗結果證明與傳統保護電路相

比，只需47% 的佈局面積便可提供高達4.8（3.3）倍的人體放電模式（機器放電模式）之

靜電放電承受能力。(4) 第四為利用動態浮接閘級技術來改善小驅動能力輸出驅動器的靜

電放電保護能力，因為小驅動能力輸出驅動器，等效只有極小的靜電放電電流旁通能力，

為了加強靜電放電保護能力，會加上一額外大的靜電放電保護元件，來旁通靜電放電電流

。但在靜電放電情形下，由於寄生電容的耦合效應，輸出級電晶體與靜電放電保護元件的

閘級會有耦合電壓，而輸出級電晶體的閘級等效是浮接的，但靜電放電保護元件的閘級則

直接接地，如此一來，小的輸出級電晶體將旁通大部份的靜電放電電流，大的靜電放電保

護元件反而只旁通小部份的靜電放電電流，因而導致小驅動能力之輸出驅動器具有極低的

靜電放電承受能力。針對此現像，動態浮接閘級技術首度被設計用來提昇此類小驅動能力

輸出驅動器之靜電放電承受能力。在靜電放電情形下，靜電放電保護元件的閘級被設計成

浮接狀態，而在積體電路正常操作時該靜電放電保護元件的閘級是等效接地的。實驗結果

證明與傳統保護電路相比，在相同的佈局面積下，該小驅動能力輸出驅動器的人體放電模

式（機器放電模式）靜電放電承受能力由原先的1KV(100V) 提昇至高達8KV(800V) 以上。

這動態浮接閘級技術也已被實際地應用於台灣積體電路公司的0.35微米及0.25微米標準元

件庫(cell library)之中。積體電路的工作電壓已自5V降低至2.5V(1.8V)，且工作頻率日

益升高，積體電路之匯流排數目也已從八位元提昇到六十四位元，這造成高輸出驅動級同

時瞬間切換的數目增加，但積體電路本身可以容許的同步切換雜訊準位卻日亦降低。本論

文的第二部份為低同步切換雜訊的輸出驅動器之設計，一改良式非對稱性爬升速率輸出驅

動器在不犧牲切換速度的狀況下，能有效地降低同步切換所造成的雜訊。本設計利用電路

技巧將高輸出驅動級分段打開以降低同步切換雜訊，但迅速關閉以降低短路電流，且能提

升運算速度，實驗結果證明此電路具有低同步切換雜訊、低功率消耗、以及高運算速度之

特點，可應用於高速、高腳位、或高輸出驅動要求的低功率金氧半積體電路上。

[摘要]

The thesis includes two parts: the first is the design on "CMOS on-chip

ESD protection circuits", and the second is the design on "low simultaneous witching

noise output buffer".　In the first part of this thesis, there are four robust

CMOS on-chip ESD protection circuits proposed: (1) The first is the complementary-LVTSCR

ESD protection circuit. One LVTSCR device merged with short-channel NMOS

and another LVTSCR device merged with short-channel PMOS in a complementary style

is designed to provide effective and direct ESD discharging paths from the input or

output pads to both the VSS and VDD power lines. The rigger voltages of the LVTSCR

devices are lowered to the snapback-breakdown voltages of the inserted short-channel NMOS

and PMOS devices. This complementary-LVTSCR ESD protection circuit provides four

different discharging paths to one-by-one bypass the four modes of ESD stresses on the pad,

so it can effectively avoid the unexpected ESD damages on the internal circuits.

Experimental results show that it can perform excellent ESD protection capability in a smaller

as compared to the conventional CMOS ESD protection circuits. The device layout area

characteristics under high-temperature environment of up to 150(C is also

experimentally investigated to guarantee the safe application of this

complementary-LVTSCR ESD protection circuit. (2) The second is a capacitor-

couple ESD protection circuit. Capacitor-couple technique is used to lower the

snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron

CMOS on-chip ESD protection circuit. The coupling capacitor can be realized by the poly

layer right under the wire-bonding metal pad without increasing extra layout

area to the pad. A timing-original design model has been derived to accurately calculate

the capacitor-couple efficiency for the ESD protection circuit. Using this capacitor-couple

ESD protection circuit, the thinner gate oxide indeep-submicron low-voltage CMOS IC's

can be effectively protected. (3) The third is a gate-coupled PTLSCR/NTLSCR ESD

protection circuit. A novel ESD protection circuit, which combines both the complementary

LVTSCR devices and the gate-coupled technique, is first proposed to effectively protect the

thinner gate oxide of deep submicron CMOS IC's without occupying large layout

area. Gate-coupled technique is used to couple the ESD-transient voltage to the

gates of the PMOS-triggered / NMOS-triggered lateral SCR (PTLSCR / NTLSCR)

devices to quickly turn on the lateral SCR devices during the ESD-stress conditions.

The trigger voltage of the gate-coupled lateral SCR devices can be significantly reduced

by the coupling  capacitor. Therefore, the thinner gate oxide of the input stages in the deep-

submicron low-voltage CMOS IC's can be fully protected against the ESD damage.

Experimental results have verified that this gate-coupled PTLSCR/NTLSCR ESD protection

circuit with a trigger voltage about7V can provide 4.8- (3.3-) times higher

Human-Body-Model (Machine-Model) ESD failure levels but only occupying 47% of

layout area, as comparing to the conventional CMOS ESD protection circuit.

(4) A novel dynamic gate-floated design is proposed to improve the ESD robustness of

the CMOS output buffers with small driving/sinking currents. This dynamic gate-

floated design can effectively solve the ESD protection issue which is due to

the different circuit connectionson the output devices. Through suitable time delay

to dynamically float the gates of the ESD-protection NMOS/PMOS in the

output buffer, the Human-Body-Model (Machine-Model) ESD failure threshold of a

2-mAoutput buffer has been successfully improved from the original 1.0KV (100V) up

to greater than 8KV(800V) in the TSMC 0.35-(m CMOS process. This dynamic gate-

floated design has been practically used in the TSMC 0.35-mm and 0.25-mm

cell libraries for general ASIC applications.　The second part is a new output

buffer  design, called as modified asymmetrical slew rate (MASR) output buffer, which

has been designed to reduce the simultaneous switching noise without

sacrificing switching speed, for high speed and heavy loading applications. The

driving capability of the output buffer is designed to sink/source 64 mA

current @ VOL/VOH = 0.4V/4.6V, with a 66 pF and 50W loading. When output

buffers switch simultaneously, the ground bounce had been specified to be less

than 0.8V for general applications. The performance of the conventional controlled-slew-rate

output buffers and this MASR output buffers had been analyzed by computer

simulation and verified by experimental test-chips. Three types of output

buffers were implemented with a 0.8mm SPDMCMOS process. When four output buffers switch

simultaneously (256 mA driving capability), the experimental results show that

the MASR buffer has the smallest ground bounce and power bounce, but the

shortest delay. This MASR output buffer is very suitable for CMOS IC's to achieve both

high-speed and high-driving applications.