摘要]

用CMOS技術所製作出來的積體電路非常容昜受靜電而損傷，尤其隨著製程技術的進步，一

些用來增加CMOS電路運作速度的技術，如通道變短、閘極氧化層變薄、金屬矽化物(

Polycide, silicide)的使用，和用來減輕熱載子效應(Hot-carrier effect)的技術，

如LDD的使用，反而使得積體電路的靜電放電(ESD)耐受能力大幅下降。

由於高功率的積體電路必須使用有別於一般低功率積體電路製程的特殊製程，在本研究論

文中，首先製作一個實驗用的測試晶片，上面有各種此製程所製作出來的元件，接下來測

量此實驗晶片上的元件其各種和靜電放電有關的特性，利用此測量出的元件特性，可用來

分析和設計有效的靜電放電保護電路。本論文主要是分析一個高功率製程積體電路的靜電

放電保護電路，利用實驗晶片上所測量出來的各個元件的特性去分析與探討此靜電放電保

護的有效性，並提出改進之道，使之能用來保護內部實際運作之電路，使其靜電放電的耐

壓度能夠符合工業應用標準。

[摘要]

The damages to CMOS VLSI circuits caused by static electronics is a very

serious issue to CMOS VLSI design technologies. Especially, as the the

technology is getting progress, the techniques that are used to improve the

operation speed of CMOS circuits such as short channel length, thinner gate

oxides, utilization of polyside and silicide, as well as the techniques to

reduce the Hot-carrier effects such as LDD(Lightly Doped Drain) dramatically

degrade the barring ability of ESD circuits.

Due to the semiconductor process difference between high power CMOS circuits

and low power CMOS circuits, we first implement a test chip with various high

power CMOS process devices, then we measure all the characteristics that are

related to ESD of the devices on the test chip. By analyzing these device

characteristics, we can charactrize the effectiveness of ESD protection

circuits and proposed new ESD protection circuits that are more efficient,

especially for circuits with high power CMOS process. The ESD protection

circuits we proposed can safely protect the CMOS circuits and make the ESD

level confined to industrial application standard.