[摘要]

本論文包括兩部分。第一部份係探討在0.18微米互補式金氧半(bulk CMOS)製程中，對於不

同的靜電放電防護佈植(ESD Implantation)與不同的佈局(Layout)設計對閘極接地之N型金

氧半場效電晶體(gate-grounded NMOS)與閘極接VDD之P型金氧半場效電晶體(gate-VDD

PMOS)的靜電放電防護能力的影響，並使靜電放電防護元件的設計達到最佳化。第二部分係

提出可避免在p/n接面形成厚場氧化層(field oxide)的新式二極體結構來提昇靜電放電防

護能力。

在積體電路製程中，為了提昇靜電放電防護元件的耐受能力，可在原製程步驟中加入額外

的靜電放電防護佈植來達到目的。本論文的第一部份針對在0.18微米互補式金氧半製程中

四種擁有不同的靜電放電防護佈植的元件，利用傳輸線觸波產生器(TLPG)來量測其二次崩

潰電流(It2)，並且比較其人體靜電放電模型(HBM)與機器靜電放電模型(MM)的靜電放電耐

受電壓，實驗數據顯示在N型金氧半場效電晶體中同時加入硼(boron)與砷(arsenic)的靜電

放電防護佈植會擁有最佳的靜電放電防護能力。

除了利用靜電放電防護佈植來提昇防護能力外，也可以利用佈局的設計來達到最佳化的效

果。在多指狀(multi-finger)金氧半場效電晶體中，如何使靜電放電電流均勻分布在每一

根防護元件上，以達到期望之最佳防護能力，成為佈局設計上的一項重要課題。本論文亦

探討在0.18微米互補式金氧半製程中，將基極(substrate)的防護圈(guard ring)深入源

極(source)區域中使每根元件擁有相同的基極電阻來達到電流均勻分布的研究，以及ESD防

護元件與電源線連接的方向對靜電放電防護能力的影響。由實驗結果證明在深次微米積體

電路的靜電放電防護元件的佈局設計上可以利用更簡單、更節省面積的佈局方式而達到更

好的靜電放電防護能力。

本論文的第二部分提出了一種新式的二極體結構，可在不需增加額外光罩的情形下，提昇

靜電放電防護耐受力。將N(P)MOS伸入二極體中，形成N(P)MOS環繞的二極體[N(P)MOS-

bounded diode]，避免在p/n接面上有厚場氧化層的形成。此部份之設計已在0.35微米互補

式金氧半製程中論證並比較此二極體結構與其他二極體和電晶體結構，尤其是在逆向偏壓

的情形下，證實此二極體結構可有效的提昇其靜電放電防護能力。本論文中的部份設計成

果已提出專利申請，並已有兩篇國際研討會論文被接受，即將發表。

[摘要]

In this thesis, the influence on ESD robustness with the different ESD

implantations and layout design on gate-grounded NMOS (GGNMOS) and gate-VDD

PMOS are investigated in a 0.18-µm salicided CMOS technology. A novel

diode structure to avoid the formation of the LOCOS (local oxidation of

silicon) field oxide isolation between the p/n junction of diode in the CMOS

process has been fabricated in a 0.35-µm polycided CMOS technology.

In the first part, the methods to sustain the higher ESD level in a 0.18-&

micro;m salicided CMOS technology are discussed. A method to enhance the ESD

robustness of the protection device is through the process design. The second

breakdown current (It2) of the NMOS devices with different ESD-implantation

solutions for on-chip ESD protection are measured by the transmission line

pulse generator (TLPG). The human-body-model (HBM) and machine-model (MM) ESD

levels of these devices are also investigated and compared. The significant

improvement is observed when the NMOS is fabricated with both boron ESD

implantation and arsenic ESD implantation. Except the ESD implantations

method, the layout design to improve uniform ESD current distribution in multi-

finger MOSFET devices for better ESD robustness in a 0.18-µm salicided

CMOS process is also investigated. The multi- finger MOSFET, without adding

the pick-up guard ring inserted into its source region, or with the vertical

direction of power line connection, can sustain a higher ESD level. The layout

of I/O cell can be drawn more compactly, but still to provide deep- submicron

CMOS IC’s with higher ESD robustness.

In the second part, a novel diode structure to enhance the ESD robustness is

discussed. A PMOS is especially inserted into the diode structure to form the

PMOS-bounded diode, which is used to block the field oxide across the p/n

junction in the diode. An NMOS is especially inserted into the diode structure

to form the NMOS-bounded diode, which is also used to block the field oxide

across the p/n junction in the diode. Without the field oxide boundary across

the p/n junction of diode structure, the proposed PMOS-bounded diode and NMOS-

bounded diode can sustain a much higher ESD stress, especially under the

reverse-biased condition. Such PMOS-bounded diode and NMOS-bounded diode are

fully process-compatible to the CMOS process without additional process

modification or mask layers. Such new diodes have been successfully verified

in a 0.35-µm LOCOS CMOS process.