[摘要]

積體電路產品之靜電放電(ESD)防護設計，隨著半導體製程技術的演進已愈來愈重要，積體

電路產品的靜電放電耐受規格並未因半導體元件的縮小而下降，因而使得晶片上之靜電放

電防護設計更加困難。先進的半導體製程技術導致互補式金氧半積體電路(CMOS IC)對ESD

的防護能力大幅地下降，因此國內外各大IC廠無不針對此一問題投入研發人力及物力，以

解決積體電路產品實際應用上必須面對的問題。

隨著高階積體電路產品對電路性能的需求：Low capacitance；Low leakage current

；Good sub-threshold I-V Characteristics；Extra low voltage operation；Low

power consumption；High radiation hardness；以及High latch-up immunity的良好特

性，使得 SOI (silicon-on-insulator)製程技術已經進展到了商業量產化的階段。而

在SOI製程技術所製作的電晶體元件，具有與基底(substrate)隔絕的特性，此種元件的散

熱能力較一般CMOS製程技術所製作的電晶體元件來的差，當SOI 元件遭受ESD侵襲時，更易

被過高的熱能所燒毀。由國外多位ESD專家的實驗結果可知，具有相同dimension的元件

在SOI製程技術下所具有的ESD保護能力要比在一般基底互補式金氧半製程技術來的低，因

此其ESD保護的問題更需要特別注意與適當的設計。

本篇論文研究方向為針對SOI製程之ESD保護課題作深入研究，以開發出更適合的ESD保護元

件及電路以應用於SOI製程上面。本篇論文共設計了四種不同結構的金氧半場效電晶體以及

三種不同結構之二極體，做不同實驗條件下靜電保護能力的比較。在金氧半場效電晶體方

面除了設計多種不同的layout參數以找出最有效的條件外，更加入了兩種靜電保護電路：

包含由閘極驅動式的靜電保護電路以及由基極驅動式的靜電保護電路。實驗結果顯示閘極

驅動式的靜電保護電路的保護能力大於由基極驅動式的靜電保護電路，此種現象反而和由

目前的CMOS製程所得到的結論不同。另外在SOI製程的二極體設計上，兩種新的二極體結構

拿來和由IBM公司所發表的Lubistor二極體做比較，實驗結果顯示新設計的兩種二極體元件

在直流的特性上，和在靜電保護能力上都要比Lubistor二極體優良，顯示新的二極體結構

具有商業化以及專利申請的價值。

[摘要]

There are two parts included in this thesis, which are related to the MOSFET

devices and diode devices in the silicon-on-insulator (SOI) CMOS technology.

In the first part, electrostatic discharge (ESD) robustness of CMOS MOSFETs

with four different layout structures of H-gate, T-gate, floating-body, and

sided-body, fabricated in a 0.15-µm partially-depleted SOI salicide CMOS

process are studied and compared. Both of the positive polarity and the

negative polarity ESD robustness of these fabricated MOSFETs are verified by

ESD tester, and the second breakdown current (It2) of these MOSFETs are also

measured by the transmission line pulse generator (TLPG). The dependences of

ESD robustness on the layout parameters of these CMOS devices in this SOI CMOS

process have been investigated to find the optimum layout rules for on-chip

ESD protection design. The effectiveness of ESD clamp circuits designed with

the gate-driven and substrate-triggered techniques are also compared in this

SOI CMOS process. The ESD robustness raised by gate-driven technique performs

more efficient than by substrate-triggered technique.

In the second part, novel gated and non-gated diode structures for ESD

protection are disclosed. The I-V characteristics of these new diodes under

forward-biased and reverse-biased conditions are measured and compared to that

of the lateral unidirectional bipolar type insulated gate transistor (

Lubistor) diode. The experimental results show that the proposed new diode

structures have an improved ESD robustness. A novel design on the power-rail

ESD clamp circuit with the gate-triggered diodes in stacked configuration has

shown a higher ESD robustness.