[摘要]

本論文提出『溫度至數位轉換器(Thermal-to-Digital Converter)』之積體電路設計。藉

由 CMOS 製程中的雙載子接面電晶體(BJT), 利用其 VEB 電壓對溫度變化的特性, 以及後

級的類比至數位轉換器, 而產生一組八位元之數位訊號, 並用二補數表示法來顯示所偵測

到的四周環境溫度。一般 CMOS 類比積體電路或者是混和訊號積體電路的設計, 均有所謂

偏差 (offset) 的問題, 本論文針對此偏差的情況下, 提出一「error bit compensation

」的補償方法, 藉由電路上的設計技巧, 加上 IC 生產上後段之 wafer test/function

test 的流程, 利用 poly-fuse 的安排與燒斷選擇, 可校正此一半導體電路因製程差異所

造成之偏差, 以增進其精確度。依本論文所提出之電路架構, 在 Hspice 電路模擬, 與

TSMC 0.35 μm 1P4M logic silicide 3.3 V 的CMOS製程實做中, 已驗證了其溫度至數位

轉換的功能, 此溫度至數位轉換器可將環境溫度, 攝氏 -20 到 +125 °C, 轉換成八位元的

數位信號輸出。

[摘要]

In this thesis, a “Thermal-to-Digital Converter” (or call as “Temperature

Sensor”) in CMOS technology has been designed by using the BJT device as the

basic thermal detector.　The ambient temperature is detected by this thermal-

to-digital converter, and presented by an 8-bit digital code in the two’s

complement format.　There are two main circuit blocks in this 8-bit thermal-to-

digital converter.　One is the front part composed of an element of the

thermal sensor and some amplifiers to enlarge the value of the detected

voltage for feeding into the rear part.　The other is the rear part which is a

sigma-delta ADC to convert the detected analog voltage into an 8-bit digital

code.　Usually, there is an offset problem in CMOS analog or mixed-signal IC

design.　In this thesis, a method called as error bit compensation is

developed to calibrate such error.　By using this method, the offset generated

from the process variation in the semiconductor circuit can be compensated.　A

test chip for this proposed thermal-to-digital converter has been fabricated

in TSMC 0.35 μm 1P4M logic silicide 3.3 V CMOS process.　From Hspice

simulation and experimental results, the proposed thermal-to-digital converter

can convert the temperature from -20 to +125 ºC into a 8-bit digital code.