[摘要]

本論文針對靜電放電防護電路的寄生效應對射頻積體電路特性的影響，分成三部份來探討

。本論文的第一部份，利用雙埠GSG實驗量測0.25微米CMOS製程中的靜電放電防護元件對射

頻訊號之增益和雜訊的影響。在不同的參數變化下，比較其靜電放電防護能力與增益損耗

和雜訊變化的關係，確認靜電放電防護電路對射頻訊號的影響大小。最後在諸多的比較資

料中，選擇最適合應用在射頻積體電路中的靜電放電防護元件。

本論文的第二部份，提出適用在射頻積體電路的靜電放電保護電路，其人體靜電放電模式

之靜電放電耐受度高達8仟伏特。藉著加入一電源線間有效的靜電放電箝制電路在射頻積體

電路中，使得射頻輸入端的靜電放電元件操作在順向導通區，而非傳統的崩潰區。藉此可

讓射頻輸入端的靜電放電元件所需之元件面積大幅地降低，來減少對輸入射頻訊號的負載

效應。這個設計已經成功地應用在900MHz的射頻接收端，並且在具有上層厚金屬的0.25微

米CMOS製程中實際晶片驗證，實驗結果顯示其人體靜電放電模式下之靜電放電耐受度可高

達8仟伏特以上。

本論文的第三部份，提出一新的射頻靜電放電防護電路設計。利用LC共振串聯來阻絕射頻

訊號因靜電放電防護電路所引起的損耗以及雜訊來源。由於電感是由最上層的厚金屬所環

繞而成，所以其可成為非常好的靜電放電電流的導通路徑。實驗結果顯示此一射頻靜電放

電防護架構對射頻訊號的影響優於傳統的二極體靜電放電防護電路。在未來射頻操作頻率

越加增高的趨勢之下，此設計將成為更適合的射頻靜電放電防護電路。

本論文之研發成果，已經提出三項美國專利申請，並已發表一篇研討會論文於2002 IEEE

RFIC Symposium 國際研討會中，另有一篇論文已被2002 VLSI Design/CAD Symposium研討

會所接受，第三篇論文並已投稿2002 Taiwan ESD Conference。

[摘要]

To reduce the parasitic effect of the ESD protection circuit devoted to RF

integrated circuits, there are three major designs proposed in this thesis. In

the first part, the two-port GSG measurement setup in the radio-frequency

region (~GHz) is used to measure the power gain S21 and noise figure from

different ESD devices in 0.25-µm CMOS process. Therefore, we can get the

relationship between RF performance and ESD level among different ESD devices.

The most suitable ESD device for RF application can be selected from the

measured data.

The second part presents a state-of-art ESD protection design for RF circuit

with a human-body-model (HBM) ESD robustness of 8kV. By including a turn-on

efficient power-rails ESD clamp circuit into the RF circuit, the ESD

protection devices of the RF input pin can be operated in the forward-biased

conduction, rather than the traditional junction breakdown condition.

Therefore, the dimension of ESD devices for the RF input pin can be further

downsized to reduce the input capacitance loading for the RF signal. This

design has been successfully applied in a 900-MHz RF receiver and fabricated

in a 0.25-µm CMOS process with a thick top metal layer. The experimental

results have confirmed that its ESD robustness is as high as 8kV under the HBM

ESD test.

In the third part, a new structure of ESD protection circuit for RF application

is proposed. The series LC-tank is used to block the signal loss and noise

figure from the ESD protection devices to the RF input pin. The inductor is

made by the top thick metal, which is suitable to conduct ESD current. The

experimental results have shown that the RF performance of ESD protection

circuit with LC-tank is superior to that of the traditional ESD protection

circuit with double diodes. The ESD protection circuit with LC-tank is more

suitable for RF application when the operation frequency becomes higher.

The research results of this thesis have been applied 3 U.S. patents.

Moreover, the contents of this thesis had also published three conference

papers. One paper had been presented in the 2002 IEEE RFIC Symposium, the

second paper has been accepted by the 2002 VLSI Design/CAD Symposium, and the

third paper has been submitted to 2002 Taiwan ESD Conference