[摘要]

雖然新的封裝技術不斷地推陳出新，線銲封裝仍是今日積體電路產品封裝型式的主流。本

論文提出三種相連貫的方法以解決在積體電路產品的應用上，銲墊所面臨的問題。

首先，在線銲封裝過程中，常會發生銲線脫落或斷裂的問題。經實驗證實，將銲墊的最上

層金屬保持不變，藉由選用適當的第二上層金屬層及連接第二上層金屬層的連接栓的佈局

圖案，即可改善線銲封裝時，銲墊固著度的問題。

再者，銲墊本身所存在的寄生電容效應，已使得在高頻電路上的設計遇到瓶頸。在前述改

善銲墊固著度問題的過程中，觸發了一個想法：改變銲墊金屬層的佈局圖案為骨架式的佈

局形式，並在金屬層下方加上擴散層，將可降低銲墊的寄生電容效應。經實驗證實此法可

以有效降低銲墊本身的寄生電容值。這個結果已經實際應用到許多的積體電路產品上。

最後，由於系統晶片時代的來臨，不僅晶片上電路的集積度愈來愈高，銲墊的個數也愈來

愈多。這使得銲墊所佔全晶片的面積比例居高不下。為提昇晶片上的有效面積使用率，將

主動元件置放於前述具骨架式金屬層佈局圖案的銲墊正下方，以節省晶片總面積將是一個

可行的方法。經本研究之實驗證實，置放於銲墊下方的N型金氧半導體電晶體，在經過不同

銲線打線力道之試驗與封裝後，其元件直流特性仍能維持在合理且可接受的範圍內。這除

了有效地節省了晶片的總面積，也使得未來靜電放電保護電路或輸出/輸入元件的設計與擺

置更加具有彈性。

[摘要]

Wire bond package is still the mainstream of IC packages although different

advanced package technologies, such as chip on board (COB), flip chip, chip

scale package (CSP), and multi-chip module (MCM), are available today. In this

thesis, there are three correlated approaches of bond pad designs of wire bond

IC products proposed for reliability improvement, parasitic capacitance

reduction, and layout area saving for system-on-a-chip (SOC) applications.

During manufacture of wire bonding in packaged IC products, the breaking of

bond wires and the peeling of bond pads occur frequently, which results open-

circuit failure in IC products. There were several prior methods reported to

overcome these problems by using additional process flows or special materials

but all with additional cost. In this thesis, a layout method is proposed to

improve the bond wire reliability in general CMOS processes. By changing the

layout patterns of bond pads, the reliability of bond wires on bond pads can

be improved. The proposed layout method for bond pad design is fully process-

compatible to general CMOS processes.

Large parasitic capacitance of conventional bond pad structure is a serious

problem in high frequency IC application. A new structure design of bond pad

is proposed to reduce its parasitic capacitance in general CMOS processes

without extra process modification. The proposed bond pad, which is modified

from the layout method for improving bond wire reliability, is constructed by

connecting multi-layer metals and inserting additional diffusion layers into

the substrate below the metal layers. The experimental results show that the

proposed low-capacitance bond pad has a capacitance less than 50% of that in

the traditional bond pad. The proposed bond pads can also keep the same good

bonding reliability as that of traditional bond pad.

To save layout area for electrostatic discharge (ESD) protection design in the

SOC era, test chip with large size NMOS devices, which are designed under bond

pads with different layout pattern designs of metal layers, was fabricated for

verification. Threshold voltage, off-state drain current, and gate leakage

current of these devices under bond pads were measured. After assembled in the

wire bond package, the measurement results show that there are only little

variations between devices under bond pads and devices beside bond pads. This

discovery can be applied on saving layout area for on-chip ESD protection

devices or I/O devices of IC products, especially when the IC’s have high pin

counts.