| [摘要] | ||
| 雖然閘極耦合靜電放電防護電路已被使用在次微米CMOS靜電放電防護電路以降低電晶體的 | ||
| 驟迴崩潰(Snapback)觸發電壓，作為改善傳統閘極接地靜電放電防護電路不均勻導通的問 | ||
| 題，但是過大的閘極耦合電壓會造成閘極氧化層的破壞反而降低靜電放電防護能力，尤其 | ||
| 是應用在深次微米CMOS製程時，這個問題將更加嚴重。本論文是針對閘極耦合靜電放電防 | ||
| 護電路之缺失加以改善，以達到最佳化之閘極耦合靜電放電防護電路設計，並在0.13微米 | ||
| CMOS製程中以SPICE模擬與測試晶片的實驗加以驗証。 | ||
| 本論文分成四部份來探討。第一部份是探討閘極接地靜電放電防護電路與閘極耦合靜電放 | ||
| 電防護電路在工作特性上的差異，並進一步探討當閘極耦合靜電放電防護電路在過大閘極 | ||
| 耦合電壓下對閘極所產生的破壞。因此，需要加上閘極電壓箝制電路以達到最佳化之閘極 | ||
| 耦合靜電放電防護電路設計。 | ||
| 本論文的第二部份，提出適用於閘極耦合靜電放電防護電路的閘極保護電路，並說明其在 | ||
| 積體電路中的輸入、輸出埠及VDD與VSS電源間的閘極耦合靜電放電防護電路設計上應用的 | ||
| 工作原理。依據靜電放電防護基本元件在遭受靜電放電衝擊下，元件結構對靜電放電耐受 | ||
| 度的影響，實際在0.13微米CMOS製程中，以變化不同的佈局參數，製作靜電放電防護電路 | ||
| 及其相關元件的測試晶片。 | ||
| 本論文的第三部份，探討閘極耦合靜電放電防護電路的大信號分析，包括三階段的操作模 | ||
| 型和設計原理。由於極性PN二極體有小的順向阻抗及順向偏壓(0.7V)特性，用單顆或數顆 | ||
| 二極體串接，並將串接二極體的陽極連接到NMOS閘極耦合靜電放電防護電路的閘極，其陰 | ||
| 極則連接到VSS，可使閘極上的靜電耦合電壓被有效的限制住，以避免產生過大的閘極耦合 | ||
| 電壓，使NMOS閘極受到破壞。同理，極性PN二極體也可用來箝制PMOS閘極耦合靜電放電防 | ||
| 護電路的閘極耦合電壓，以避免PMOS閘極被過大的閘極耦合電壓破壞。HSPICE的參數模擬 | ||
| 可被用來驗証設計的電路，並由驗証的結果決定適合的耦合電容值、維持電阻值和箝制二 | ||
| 極體的大小及串接數量，使閘極耦合靜電放電防護電路設計不僅不影響正常的電路操作， | ||
| 且在靜電放電過程中，閘極受到保護，達到設計最佳化的目的。 | ||
| 本論文的第四部份是實驗結果的量測與分析。其中閘極耦合靜電放電防護電路的靜電防護 | ||
| 能力優於閘極接地靜電放電防護電路，可經由靜電放電實驗中電晶體的二次崩潰點( | ||
| Second Breakdown)的量測和靜電放電的測試結果清楚地被驗証。 通道寬長比200/0.25的 | ||
| NMOS閘極耦合靜電放電防護電路，在人體放電模型測試及機器放電模型測試中，其最大靜 | ||
| 電放電防護能力各別可大於3kV和200V。 之於通道寬長比600/0.25的NMOS閘極耦合靜電放 | ||
| 電防護電路，則各別可高於8kV和700V。 | ||
| 經由本論文之研究結果，使用串接數個大尺寸的箝制二極體，保護閘極耦合靜電放電防護 | ||
| 電路的閘極，除可保持原來設計的導通時間外，還可以有效箝制 閘極耦合過大電壓，提昇 | ||
| 原設計的靜電放電防護能力。 | ||
| [摘要] | ||
| Gate-coupled technique has been used to lower device breakdown voltage and to | ||
| ensure uniform ESD (ElectroStatic Discharge) current distribution in deep- | ||
| submicron CMOS on-chip ESD protection circuit. But, the gate-coupled design | ||
| has also been confirmed to cause a sudden degradation on ESD robustness of the | ||
| ESD protection devices in deep-submicron 0.35-µm and 0.18-µm | ||
| silicide blocking CMOS technologies. This thesis is to investigate the | ||
| optimization of the ESD protection circuit with gate-coupled design, and prove | ||
| that the optimized gate-coupled ESD protection design can be used to | ||
| continually improve the ESD robustness of protection devices in the deep- | ||
| submicron 0.13-µm silicide blocking CMOS technology. By using this gate- | ||
| coupled ESD protection circuit, the thinner gate oxide of CMOS devices in deep- | ||
| submicron low-voltage CMOS ASIC can be effectively protected from ESD events. | ||
| This thesis includes the four main parts. The first part is to introduce why | ||
| the gate-coupled ESD protection is better than the traditional gate-grounded | ||
| ESD protection circuit. However, the higher coupled gate voltage will cause | ||
| the gate oxide damage and degrade the ESD immunity. The coupled gate voltage | ||
| on the gate-coupled NMOS device can be limited with a voltage clamp circuit to | ||
| prevent the overstress gate-driven effect during ESD transient. | ||
| The second part of this thesis is to introduce the application of this | ||
| proposed design, which can be used to protect the input pin, output pin and | ||
| power rail of the integrated circuits. Test chips with the proposed ESD | ||
| protection design has been fabricated in a deep-submicron 0.13-µm CMOS | ||
| process. | ||
| The third part is the verification results of the characteristics of the | ||
| proposed gate-coupled ESD protection circuit with gate clamping diodes. It is | ||
| to find out the dependence of the turn-on time and the gate-coupled voltage, | ||
| which has correlation with the sustaining resistance, coupling capacitance, | ||
| NMOS channel width/length and clamping diode dimension. Therefore, the | ||
| adequate device dimension for the robustness ESD design can be determined. | ||
| The final part is the analysis on the experimental results comparing with the | ||
| SPICE simulation results. Through the verification of the second breakdown | ||
| current (It2) measurement and ESD-stress test, it is clearly seen that the | ||
| gate-coupled ESD protection circuit is better than the gate-grounded ESD | ||
| protection circuit. The HBM (Human Body Model) and MM (Machine Model) ESD | ||
| immunity of the proposed NMOS gate-coupled ESD protection circuit with the | ||
| NMOS channel width/length (W/L) in 200/0.25 are higher than 3kV and 200V, | ||
| respectively. For the gate-coupled ESD protection circuit with NMOS W/L=600/0. | ||
| 25, it can sustain HBM and MM ESD level up to 8kV and 700V. | ||
| Base on the study results, using the larger size of gate clamping diode string | ||
| for protecting the gate oxide of the gate-coupled NMOS transistor has better | ||
| ESD immunity with the same turn-on time as the one of original design and | ||
| lower coupled gate voltage. |