[摘要]

本篇論文主旨在設計適用於寬頻電路的靜電放電防護電路。其原理為利用元件或電路特性，使靜電放電防護電路對原電路的影響降到最低，但又能具有高水準之靜電放電防護能力。本論文共有三個設計子項，共下線了三顆晶片來驗證這些設計。

第一個設計為利用遞減面積分散式元件來做靜電放電防護，並利用屏蔽共平面導波管來分隔這些元件，以達到很好的寬頻阻抗匹配。又因為最接近輸入端的靜電放電防護元件擁有最大的面積，可以承受比較大的靜電放電功率，所以靜電放電的防護能力相對於傳統的等面積分散式靜電防護電路可以被大幅的提升，實驗結果顯示新設計的靜電放電電路可以承受人體放電模式靜電放電轟擊超過八千伏特。

第二個設計為使用p型結構的防護架構，讓靜電放電電流在輸入端一進來就看到一組靜電放電防護元件，以達成有效的靜電放電防護能力。搭配一條特定長度的屏蔽共平面導波管和一組接近核心電路的靜電放電防護元件的組合，此電路相對於傳統的等面積分散式靜電放電防護電路，在寬頻阻抗匹配上可以擁有更好的表現。實驗結果亦顯示第二個設計之p型結構靜電放電防護電路可以承受人體放電模式靜電放電轟擊超過八千伏特。

第三個設計為製作一個分散式寬頻放大器，並在其中加入等面積或遞減面積分散式的靜電放電防護電路，來觀察靜電放電防護能力的增加程度，和電路性能的差異。分散式寬頻放大器搭配等面積分散式的靜電放電防護電路可以達到不錯的寬頻表現（增益從十億赫茲到一百億赫茲間在4.7 ± 1 dB間變化）和靜電放電防護能力（人體放電模式的靜電放電防護能力約五千五百伏特，機器放電模式的靜電放電防護能力約三百二十五伏特和充電元件放電模式的靜電放電防護能力約五百伏特）。而分散式寬頻放大器搭配遞減面積分散式的靜電放電防護電路，除了也可以達到不錯的寬頻表現（增益從十億赫茲到九十億赫茲間在5.0 ± 1.1 dB間變化），又更進一步增強了靜電放電防護能力（人體放電模式的靜電放電防護能力超過八千伏特，機器放電模式的靜電放電防護能力約五百七十五伏特和充電元件放電模式的靜電放電防護能力約六百五十伏特）。

本論文之研究成果已經撰寫成三篇研討會論文，投稿到國際研討會去，更詳細之研究方法與實驗結果也將整理成長篇論文投稿到國際期刊中。

[Abstract]

The aim in this thesis is to design the ESD protection circuits which are suitable in broadband RF circuits. The ESD protection ability and the influence to the performance of the broadband RF circuit after inserting the ESD protection circuit needs to be considered simultaneously. This thesis includes three topics, which were verified through 3 individual chips.

In the first topic, a new distributed ESD protection structure is proposed to achieve both good ESD and RF performance. The proposed decreasing-size distributed ESD (DS-DESD) protection circuit is constructed by arranging ESD protection stages with decreasing device-size and separating them by the coplanar waveguides with ground shield (CPWG). The scheme is not only beneficial to the broadband RF performance, but also to the ESD protection ability (human-body-model (HBM) ESD protection level over 8 kV).

In the second topic, as a p model in ac analysis, the proposed p-model distributed ESD (p-DESD) protection circuit, composed of one pair of ESD components near the I/O pin, the other pair close to the core circuit, and a CPWG connecting these two pairs, can successfully achieve both the great ESD protection ability (HBM ESD level over 8 kV) and excellent broadband RF impedance match.

In the third topic, two distributed ESD protection structures are presented and applied to DAs. Fabricated in a standard 0.25-mm CMOS process, the DA with the first ES-DESD protection structure, contributing extra 300 fF parasitic capacitance to the circuit, can sustain the HBM ESD level of 5.5 kV, the machine-model (MM) ESD level of 325 V and the charged-device-model (CDM) ESD level of 500 V, and exhibits the flat-gain of 4.7 ± 1 dB over the bandwidth from 1 to 10 GHz. With the same amount of the parasitic capacitance, the DA with the second DS-DESD protection achieves a better ESD robustness, the HBM ESD level over 8 kV, the MM ESD level of 575 V and the CDM ESD level of 650 V, and performs the flat-gain of 5.0 ± 1.1 dB over the bandwidth from 1 to 9 GHz. With these two proposed ESD protections, the broadband performances of the DAs are acceptable, yet the ESD protection abilities are excellent.