[Referred_Journal_Papers]  [International_Conference_Papers]  [Local_Journal_and_Conference_Papers]

[Invited_Talks_and_Courses]  [US_Patents]  [Taiwan_Patents]  [China_Patents]  [Book_Chapters]

[1]

C.-C. Ker, Chun-Yu Lin, M.-D. Ker, H.-J. Chen, and Y.-F. Hsieh, “Bidirectional gate-to-source ESD protection circuit with adjustable turn-on voltage for GaN-on-silicon power HEMT,” IEEE International Symposium on Power Semiconductor Devices and ICs, 2026.

[2]

H.-Y. Lee, H.-E. Cheng, and Chun-Yu Lin, “Compact inverter-triggered SCR for ESD protection in broadband communication circuits,” IEEE International Symposium on Circuits and Systems, 2026.

[3]

C.-C. Ker, Chun-Yu Lin, C.-Y. Ke, and M.-D. Ker, “Design on power-rail ESD clamp circuit to reduce standby leakage current in GaN-on-Si process,” International VLSI Symposium on Technology, Systems and Applications, 2026.

[4]

C.-C. Ker, Chun-Yu Lin, M.-D. Ker, Y.-H. Chang, C.-W. Li, T.-Y. Chiang, and C.-C. Wang, “On-die bidirectional ESD protection circuit for GaN-on-silicon power HEMT,” IEEE International Reliability Physics Symposium, 2026.

[5]

C.-H. Chiang and Chun-Yu Lin, “The influence of skin effect on metal lines in ESD protection circuit,” IEEE International Conference on Microelectronic Test Structures, 2026.

[6]

C.-C. Ker, C.-W. Hsu, Chun-Yu Lin, M.-D. Ker, C.-C. Wang, and T.-Y. Chiang, “Dependence of N-well guard ring bias on latch-up failure level in a HV/LV mixed-voltage CMOS IC,” International VLSI Symposium on Technology, Systems and Applications, 2025. (榮獲 Best Poster Award)

[7]

E.-W. Chien, H.-E. Cheng, and Chun-Yu Lin, “Study of silicide blocking for GGNMOS performance and turn-on time in CMOS process,” IEEE International Conference on Consumer Electronics - Taiwan, 2024, pp. 783-784.

[8]

C.-C. Chen and Chun-Yu Lin, “A bidirectional ESD protection circuit with high reliability and low leakage for consumer electronic products,” IEEE International Conference on Consumer Electronics - Taiwan, 2024, pp. 789-790.

[9]

Y.-S. Hou and Chun-Yu Lin, “On the study of ESD-induced electromigration in CMOS metallization,” International Conference on Solid State Devices and Materials, 2023, pp. 705-706.

[10]

C.-L. Wu and Chun-Yu Lin, “Power-rail ESD clamp circuit for the 3×VDD power pin of negative voltage application,” Taiwan and Japan Conference on Circuits and Systems, 2023.

[11]

P.-X. Chen and Chun-Yu Lin, “Ultra-low-leakage ESD power clamp circuit with double detection mechanism,” Taiwan and Japan Conference on Circuits and Systems, 2023.

[12]

Chun-Yu Lin, C.-Y. Hsieh, Z.-J. Dai, and Y.-H. Lai, “ESD protection design for fan-out panel-level packaging,” International EOS/ESD Symposium on Design and System, 2022.

[13]

Chun-Yu Lin, B.-Y. Li, and Y.-Q. Fu, “Study of RC-diode ESD protection circuit for high-frequency applications,” International EOS/ESD Symposium on Design and System, 2022.

[14]

W.-C. Liao, C.-Y. Liu, and Chun-Yu Lin, “On the study of impact of temperature on ESD protection device,” International Electron Devices and Materials Symposium, 2022.

[15]

Y.-Q. Fu, J.-Y. Wang, and Chun-Yu Lin, “ESD protection design for 24GHz and 60GHz dual-band application in CMOS technology,” International Electron Devices and Materials Symposium, 2018.

[16]

M.-T. Lin and Chun-Yu Lin, “Improved ESD protection design for high-frequency applications in CMOS technology,” International Conference on Infrared, Millimeter, and Terahertz Waves, 2018.

[17]

B.-W. Peng and Chun-Yu Lin, “Low-loss I/O pad with ESD protection for K/Ka-bands applications in nanoscale CMOS process,” IEEE International Symposium on Integrated Circuits and Systems, 2018.

[18]

J.-Y. Wang, Y.-Q. Fu, and Chun-Yu Lin, “ESD protection design for 24-GHz and 60-GHz dual-band applications in CMOS technology,” Taiwan and Japan Conference on Circuits and Systems, 2018.

[19]

W.-H. Fu and Chun-Yu Lin, “ESD protection diode strings for IC chips of miniature robot applications,” International Conference on Recent Innovations in Engineering and Technology, 2018.

[20]

Chun-Yu Lin and Y.-L. Chiu, “High-voltage driving circuit with on-chip ESD protection in CMOS technology,” International Conference on Intelligent Informatics and BioMedical Sciences, 2017, pp. 223-224.

[21]

Y.-H. Lai and Chun-Yu Lin, “π-model SCR device for ESD protection in gigahertz CMOS ICs,” International Electron Devices and Materials Symposium, 2017, pp. 301-302.

[22]

B.-W. Peng and Chun-Yu Lin, “Low-loss I/O pad with ESD protection devices for gigahertz applications in CMOS technology,” International Electron Devices and Materials Symposium, 2017, pp. 303-304.

[23]

Chun-Yu Lin and Y.-L. Chiu, “Investigation on stacked-device output driver with SCR ESD protection in nanoscale CMOS process,” Taiwan and Japan Conference on Circuits and Systems, 2017, p. 24.

[24]

M.-D. Ker, Chun-Yu Lin, Y.-H. Wu, and W.-T. Wang, “ESD protection design with low-leakage consideration for silicon chips of IoT applications,” IEEE International Conference on CYBER Technology in Automation, Control, and Intelligent Systems, 2017.

[25]

M.-T. Lin and Chun-Yu Lin, “K-band low-noise amplifier with stacked-diode ESD protection in nanoscale CMOS technology,” IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 2017.

[26]

Chun-Yu Lin and M.-T. Lin, “ESD protection design with stacked diodes and local power clamp for silicon chips of high-speed applications,” International Conference on Natural Sciences and Engineering, 2017, pp. 136-137.

[27]

Chun-Yu Lin and R.-K. Chang, “ESD protection design for high-speed circuits in nanoscale CMOS process,” International Symposium on Integrated Circuits, 2016.

[28]

M.-T. Lin, G.-Y. Li, and Chun-Yu Lin, “Diodes string with embedded SCR for RF ESD protection in 0.18-um CMOS,” International Electron Devices and Materials Symposium, 2016.

[29]

G.-L. Huang, W.-H. Fu, and Chun-Yu Lin, “Vertical NPN devices for ESD protection in BiCMOS technology,” International Electron Devices and Materials Symposium, 2016.

[30]

G.-Y. Li and Chun-Yu Lin, “On-chip ESD protection design for radio-frequency power amplifier with large-swing-tolerance consideration,” IEEE Asia Pacific Conference on Circuits and Systems, 2016, pp. 258-261.

[31]

J.-T. Chen, Chun-Yu Lin, R.-K. Chang, M.-D. Ker, T.-C. Tzeng, and T.-C. Lin, “ESD protection design for high-speed applications in CMOS technology,” IEEE Midwest Symposium on Circuits and Systems, 2016, pp. 309-312.

[32]

Chun-Yu Lin, R.-K. Chang, and M.-D. Ker, “A gigahertz low-noise amplifier with ESD protection in nanoscale CMOS technology,” Asia-Pacific International Symposium on Electromagnetic Compatibility, 2016.

[33]

Chun-Yu Lin, R.-H. Liu, and M.-D. Ker, “ESD self-protection design on 2.4-GHz T/R switch for RF application in CMOS process,” IEEE International Reliability Physics Symposium, 2016.

[34]

Chun-Yu Lin and R.-K. Chang, “Test structures of LASCR device for RF ESD protection in nanoscale CMOS process,” IEEE International Conference on Microelectronic Test Structures, 2016, pp.100-103.

[35]

Chun-Yu Lin, M.-D. Ker, P.-H. Chang, and W.-T. Wang, “Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology,” IEEE Nanotechnology Materials and Devices Conference, 2015, pp. 63-66.

[36]

Chun-Yu Lin, P.-H. Chang, R.-K. Chang, M.-D. Ker, and W.-T. Wang, “Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology,” IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 2015.

[37]

Chun-Yu Lin, M.-L. Fan, and W.-H. Fu, “ESD protection design for gigahertz differential LNA in a 65-nm CMOS process,” Asia-Pacific International Symposium on Electromagnetic Compatibility, 2015.

[38]

M.-D. Ker, Chun-Yu Lin, and T.-Y. Yang, “Circuit design of electrical stimulator realized in 0.18μm CMOS process for epileptic seizure suppression,” International Brain Stimulation Conference, 2015.

[39]

C.-Y. Wu, H. Chiueh, M.-D. Ker, Y.-L. Hsin, S.-F. Liang, F.-Z. Shaw, Chun-Yu Lin, and W.-M. Chen, “Closed-loop stimulation and control of epileptic seizures in an implantable neural-prosthetic device,” International Brain Stimulation Conference, 2015.

[40]

Chun-Yu Lin, “ESD protection designs on integrated circuits with very low parasitic capacitance for wireless communication applications,” Tokyo International Conference on Engineering and Applied Science, 2014, pp. 1115-1116.

[41]

Chun-Yu Lin and Y.-L. Chiu, “Dual-directional silicon-controlled rectifier device for ESD protection in biomedical integrated circuits,” International Electron Devices and Materials Symposium, 2014.

[42]

C.-Y. Wu, H. Chiueh, M.-D. Ker, Y.-L. Hsin, S.-F. Liang, F.-Z. Shaw, Chun-Yu Lin, T.-J. Chen, Y.-L. Wang, and W.-M. Chen, “On the design of a closed-loop neural-prosthetic 0.18um CMOS SoC for real-time epileptic seizure control,” Workshop on Biomedical Microelectronic Translational Systems, 2014.

[43]

K.-Y. Lin, M.-D. Ker, and Chun-Yu Lin, “Design of electrical stimulator with high-voltage-tolerant stimulus driver in a 0.18μm low-voltage CMOS process,” Workshop on Biomedical Microelectronic Translational Systems, 2014.

[44]

C.-Y. Wu, H. Chiueh, M.-D. Ker, Y.-L. Hsin, S.-F. Liang, F.-Z. Shaw, T.-J. Chen, Chun-Yu Lin, Y.-L. Wang, W.-M. Chen, and W. Liu, “A closed-loop neural-prosthetic device for real-time epileptic seizure control,” Neural Interfaces Conference, 2014.

[45]

Chun-Yu Lin, M.-L. Fan, M.-D. Ker, L.-W. Chu, J.-C. Tseng, and M.-H. Song, “Improving ESD robustness of stacked diodes with embedded SCR for RF applications in 65-nm CMOS,” IEEE International Reliability Physics Symposium, 2014.

[46]

K.-Y. Lin, M.-D. Ker, and Chun-Yu Lin, “A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant,” IEEE International Symposium on Circuits and Systems, 2014, pp. 237-240.

[47]

L.-W. Chu, Chun-Yu Lin, M.-D. Ker, M.-H. Song, J.-C. Tseng, C.-P. Jou, and M.-H. Tsai, “ESD protection design for wideband RF applications in 65-nm CMOS process,” IEEE International Symposium on Circuits and Systems, 2014, pp. 1480-1483.

[48]

Chun-Yu Lin and R.-K. Chang, “On-chip ESD protection designs with SCR-based devices in RF integrated circuits,” IEEE International Conference on Consumer Electronics - Taiwan, 2014, pp. 15-16.

[49]

Chun-Yu Lin, L.-W. Chu, S.-Y. Tsai, M.-D. Ker, M.-H. Song, C.-P. Jou, T.-H. Lu, J.-C. Tseng, M.-H. Tsai, T.-L. Hsu, P.-F. Hung, Y.-L. Wei, and T.-H. Chang, “ESD protection design for radio-frequency integrated circuits in nanoscale CMOS technology,” IEEE International Conference on Nanotechnology, 2013, pp. 241-244.

[50]

M.-D. Ker and Chun-Yu Lin, “On-chip ESD protection designs in RF integrated circuits for radio and wireless applications,” IEEE International Conference on Electron Devices and Solid-State Circuits, 2013.

[51]

Chun-Yu Lin and M.-D. Ker, “SCR device for on-chip ESD protection in RF power amplifier,” IEEE International Conference on Electron Devices and Solid-State Circuits, 2013.

[52]

W.-M. Chen, H. Chiueh, T.-J. Chen, C.-L. Ho, C. Jeng, S.-T. Chang, M.-D. Ker, Chun-Yu Lin, Y.-C. Huang, T.-Y. Fan, M.-S. Cheng, C.-W. Chou, S.-F. Liang, T.-C. Chien, S.-Y. Wu, Y.-L. Wang, F.-Z. Shaw, Y.-H. Huang, C.-H. Yang, J.-C. Chiou, C.-W. Chang, L.-C. Chou, and C.-Y. Wu, “A fully-integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, 2013, pp. 286-287.

[53]

M.-H. Tsai, H.-H. Hsieh, Chun-Yu Lin, L.-W. Chu, S.-H. Hsu, J.-D. Jin, T.-J. Yeh, C.-P. Jou, F.-L. Hsueh, and M.-D. Ker, “A 56-67 GHz low-noise amplifier with 5.1-dB NF and 2.5-kV HBM ESD protection in 65-nm CMOS,” Asia-Pacific Microwave Conference, 2012, pp. 747-749.

[54]

S.-Y. Tsai, Chun-Yu Lin, L.-W. Chu, and M.-D. Ker, “Design of ESD protection for RF CMOS power amplifier with inductor in matching network,” IEEE Asia Pacific Conference on Circuits and Systems, 2012, pp. 467-470.

[55]

Y.-C. Huang, M.-D. Ker, and Chun-Yu Lin, “Design of negative high voltage generator for biphasic stimulator with SoC integration consideration,” IEEE Biomedical Circuits and Systems Conference, 2012, pp. 29-32.

[56]

M.-D. Ker, W.-L. Chen, and Chun-Yu Lin, “Live Demonstration: Implantable stimulator for epileptic seizure suppression with loading impedance adaptability,” IEEE Biomedical Circuits and Systems Conference, 2012, p. 78.

[57]

L.-W. Chu, Chun-Yu Lin, S.-Y. Tsai, M.-D. Ker, M.-H. Song, C.-P. Jou, T.-H. Lu, J.-C. Tseng, M.-H. Tsai, T.-L. Hsu, P.-F. Hung, T.-H. Chang, and Y.-L. Wei, “Design of ESD protection cell for dual-band RF applications in a 65-nm CMOS process,” Electrical Overstress / Electrostatic Discharge Symposium, 2012, pp. 331-335.

[58]

Chun-Yu Lin, Y.-J. Li, Y.-C. Huang, and M.-D. Ker, “Design of high-voltage-tolerant stimulus driver for epileptic seizure suppression in a 0.18-μm CMOS process,” Neural Interfaces Conference, 2012, p. 154.

[59]

Chun-Yu Lin, Y.-J. Li, and M.-D. Ker, “High-voltage-tolerant stimulator with adaptive loading consideration for electronic epilepsy prosthetic SoC in a 0.18-μm CMOS process,” IEEE International NEWCAS Conference, 2012, pp. 125-128.

[60]

L.-W. Chu, Chun-Yu Lin, S.-Y. Tsai, M.-D. Ker, M.-H. Song, C.-P. Jou, T.-H. Lu, J.-C. Tseng, M.-H. Tsai, T.-L. Hsu, P.-F. Hung, and T.-H. Chang, “Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology,” IEEE International Symposium on Circuits and Systems, 2012, pp. 2127-2130.

[61]

Chun-Yu Lin, L.-W. Chu, M.-D. Ker, M.-H. Song, C.-P. Jou, T.-H. Lu, J.-C. Tseng, M.-H. Tsai, T.-L. Hsu, P.-F. Hung, and T.-H. Chang, “ESD protection structure with inductor-triggered SCR for RF applications in 65-nm CMOS process,” IEEE International Reliability Physics Symposium, 2012.

[62]

Chun-Yu Lin, L.-W. Chu, S.-Y. Tsai, M.-D. Ker, T.-H. Lu, T.-L. Hsu, P.-F. Hung, M.-H. Song, J.-C. Tseng, T.-H. Chang, and M.-H. Tsai, “Modified LC-tank ESD protection design for 60-GHz RF applications,” European Conference on Circuit Theory and Design, 2011, pp. 57-60.

[63]

M.-D. Ker and Chun-Yu Lin, “ESD protection consideration in nanoscale CMOS technology,” IEEE International Conference on Nanotechnology, 2011, pp. 720-723.

[64]

M.-D. Ker, W.-L. Chen, and Chun-Yu Lin, “Adaptable stimulus driver for epileptic seizure suppression,” IEEE International Conference on Integrated Circuit Design & Technology, 2011.

[65]

M.-D. Ker, Chun-Yu Lin, and T.-L. Chang, “Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process,” IEEE International Symposium on VLSI Design, Automation and Test, 2011, pp. 374-377.

[66]

M.-D. Ker, Chun-Yu Lin, and T.-L. Chang, “Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process,” IEEE International Reliability Physics Symposium, 2011, pp. 717-718.

[67]

W.-L. Chen, Chun-Yu Lin, and M.-D. Ker, “Design of stimulus driver to suppress epileptic seizure with adaptive loading consideration,” IEEE International Symposium on Next-Generation Electronics, 2010, pp. 9-12.

[68]

M.-D. Ker, Y.-R. Wen, W.-Y. Chen, and Chun-Yu Lin, “Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process,” IEEE International Symposium on Next-Generation Electronics, 2010, pp. 100-103.

[69]

Chun-Yu Lin and M.-D. Ker, “Modeling the parasitic capacitance of ESD protection SCR to co-design matching network in RF ICs,” IEEE International Symposium on Next-Generation Electronics, 2010, pp. 104-107.

[70]

Chun-Yu Lin and M.-D. Ker, “Dual SCR with low-and-constant parasitic capacitance for ESD protection in 5-GHz RF integrated circuits,” IEEE International Conference on Solid-State and Integrated Circuit Technology, 2010, pp. 707-709.

[71]

Chun-Yu Lin and M.-D. Ker, “CDM ESD protection design with initial-on concept in nanoscale CMOS process,” IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 2010, pp. 193-196.

[72]

M.-D. Ker, W.-L. Chen, Chun-Yu Lin, and Y.-H. Weng, “Circuit design of stimulus driver for adaptive loading applications,” Neural Interfaces Conference, 2010, p. 125.

[73]

Chun-Yu Lin, M.-D. Ker, and Y.-W. Hsiao, “ESD protection design for differential low-noise amplifier with cross-coupled SCR,” IEEE International Conference on Integrated Circuit Design & Technology, 2010, pp. 39-42.

[74]

Chun-Yu Lin and M.-D. Ker, “2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process,” IEEE International Symposium on Circuits and Systems, 2010, pp. 3417-3420.

[75]

Chun-Yu Lin, L.-W. Chu, M.-D. Ker, T.-H. Lu, P.-F. Hung, and H.-C. Li, “Self-matched ESD cell in CMOS technology for 60-GHz broadband RF applications,” IEEE Radio Frequency Integrated Circuit Symposium, 2010, pp. 573-576.

[76]

Chun-Yu Lin and M.-D. Ker, “Low-capacitance and low-loss bond pad design using LC-resonator structure in CMOS technology for RF and high-speed applications,” International Conference on Solid State Devices and Materials, 2009, pp. 372-373.

[77]

Chun-Yu Lin and M.-D. Ker, “Co-design strategy with low-C consideration for on-chip ESD protection in RF ICs,” International PhD Student Workshop on SOC, 2008.

[78]

Chun-Yu Lin and M.-D. Ker, “Optimization on SCR device with low capacitance for on-chip ESD protection in UWB RF circuits,” IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 2008, pp. 58-61.

[79]

M.-D. Ker, Chun-Yu Lin, and G.-X. Meng, “ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR,” IEEE International Symposium on Circuits and Systems, 2008, pp. 1292-1295.

[80]

Chun-Yu Lin and M.-D. Ker, “ESD protection design for RF circuits in CMOS technology with low-C implementation,” International Semiconductor Technology Conference, 2008, pp. 70-75.

[81]

Chun-Yu Lin and M.-D. Ker, “Low-capacitance SCR with waffle layout structure for on-chip ESD protection in RF ICs,” IEEE Radio Frequency Integrated Circuit Symposium, 2007, pp. 749-752.

[82]

M.-D. Ker and Chun-Yu Lin, “Test structure on SCR device in waffle layout for RF ESD protection,” IEEE International Conference on Microelectronic Test Structures, 2007, pp.196-199.