[Referred_Journal_Papers]  [International_Conference_Papers]  [Local_Journal_and_Conference_Papers]

[Invited_Talks_and_Courses]  [US_Patents]  [Taiwan_Patents]  [China_Patents]  [Book_Chapters]

[1]

“(Keynote) Low-Capacitance ESD Protection for High-Speed Circuits and Systems,” Pan-Asia Conference on Circuits and Systems, Sep. 10, 2026.

[2]

“ESD Protection Design Challenges for > 100Gbps High-Speed Interfaces,” 可靠度驗證技術與高速介面ESD研討會, Jun. 17, 2026.

[3]

“晶片前瞻技術模組教師經驗分享演講,” 教育部先進製程IC設計人才培育計畫, Mar. 4, 2026.

[4]

“On-Chip Low-C ESD Protection Designs for High-Speed and High-Frequency (FinFET) Applications,” Analog IC Workshop, Sep. 13, 2025.

[5]

“高速積體電路之CDM防護設計,” 聯〇半導體, Jul. 17, 2025.

[6]

“ESD Protection Design for High-Speed ICs,” Taiwan ESD Workshop, Aug. 20, 2024.

[7]

“高速積體電路之ESD防護設計,” 聯〇半導體, Mar. 7 and 14, 2024.

[8]

“ESD Protection Design for IC Products,” 國立臺灣大學電機資訊學院電信工程學研究所, Oct. 20, 2021.