[Referred_Journal_Papers]  [International_Conference_Papers]  [Local_Journal_and_Conference_Papers]

[Invited_Talks_and_Courses]  [US_Patents]  [Taiwan_Patents]  [China_Patents]  [Book_Chapters]

[1]

K.-Y. Chen, S.-H. Wu, P.-X. Chen, and Chun-Yu Lin, “2xVDD-tolerant ESD clamp with dual detection and ultra-low leakage,” IEEE J. Electron Devices Society, vol. 14, pp. 205-212, Apr. 2026, doi: 10.1109/JEDS.2026.3674432

[2]

Chun-Yu Lin and M.-D. Ker, “ESD protection design: fundamentals and advanced strategies,” IEEE Open J. Solid-State Circuits Society, vol. 6, pp. 61-76, Mar. 2026, doi: 10.1109/OJSSCS.2026.3667840

[3]

C.-C. Ker, Chun-Yu Lin, M.-D. Ker, T.-Y. Chiang, C.-C. Wang, and R. Jiang, “Cost-efficient bidirectional ESD protection for 650-V GaN power HEMT with co-packaged transient voltage suppressor,” IEEE Trans. Device and Materials Reliability, vol. 26, no. 1, pp. 235-243, Mar. 2026, doi: 10.1109/TDMR.2025.3640734

[4]

Chun-Yu Lin, “Review of low-C ESD protection designs for high-speed and high-frequency applications,” IEEE Trans. Electron Devices, vol. 72, no. 12, pp. 6411-6422, Dec. 2025, doi: 10.1109/TED.2025.3625953

[5]

H.-E. Cheng and Chun-Yu Lin, “Power-clamp-triggered SCR for broadband RF ESD protection,” IEEE Trans. Electron Devices, vol. 72, no. 12, pp. 6460-6465, Dec. 2025, doi: 10.1109/TED.2025.3617031

[6]

C.-C. Ker, Chun-Yu Lin, M.-D. Ker, Y.-H. Chang, C.-W. Li, T.-Y. Chiang, and C.-C. Wang, “Gate-to-source ESD protection design for GaN-on-silicon power HEMT,” Microelectronics Reliability, vol. 175, Dec. 2025, doi: 10.1016/j.microrel.2025.115948

[7]

C.-Y. Liang, H.-H. Wang, and Chun-Yu Lin, “Compact ESD protection device for separated power domain application,” IEEE Trans. Electron Devices, vol. 72, no. 11, pp. 5830-5837, Nov. 2025, doi: 10.1109/TED.2025.3608741

[8]

H.-E. Cheng, C.-L. Wu, and Chun-Yu Lin, “3xVDD-tolerant power-rail ESD clamp circuit for negative mixed-voltage interfaces,” Solid-State Electronics, vol. 229, Nov. 2025, doi: 10.1016/J.SSE.2025.109185

[9]

C.-Y. Hsieh and Chun-Yu Lin, “All-NMOS power-rail ESD clamp circuit with compact area and low leakage,” IEEE Trans. Electron Devices, vol. 71, no. 9, pp. 5205-5211, Sep. 2024, doi: 10.1109/TED.2024.3434776

[10]

Y.-S. Hou and Chun-Yu Lin, “Characterization of ESD-induced electromigration on CMOS metallization in on-chip ESD protection circuit,” Japanese Journal of Applied Physics, vol. 63, no. 2, Feb. 2024, doi: 10.35848/1347-4065/ad1776

[11]

C.-R. Chang and Chun-Yu Lin, “Power-line-triggered ESD protection SCR for 0–20 GHz applications in CMOS technology,” IEEE Trans. Electron Devices, vol. 70, no. 12, pp. 6103-6109, Dec. 2023, doi: 10.1109/TED.2023.3320985

[12]

C.-C. Lin and Chun-Yu Lin, “ESD research of SCR devices under harsh environments,” Materials, vol. 16, no. 18, Sep. 2023, doi: 10.3390/ma16186182

[13]

C.-R. Chang, Z.-J. Dai, and Chun-Yu Lin, “π-shape ESD protection design for multi-Gbps high-speed circuits in CMOS technology,” Materials, vol. 16, no. 7, Mar. 2023, doi: 10.3390/ma16072562

[14]

Chun-Yu Lin and Y.-Q. Fu, “RC-diode ESD protection design for high-frequency applications,” Solid-State Electronics, vol. 188, Feb. 2022, doi: 10.1016/J.SSE.2021.108222

[15]

R.-K. Chang, Chun-Yu Lin, and M.-D. Ker, “Design of Fin-diode-triggered rotated silicon-controlled rectifier for high-speed digital application in 16-nm FinFET process,” IEEE Trans. Electron Devices, vol. 67, no. 7, pp.2725-2731, Jul. 2020, doi: 10.1109/TED.2020.2995145

[16]

Chun-Yu Lin, Y.-Q. Fu, and J.-Y. Wang, “Compact ESD protection cell for multi-band millimeter-wave applications,” IEEE Microwave and Wireless Components Letters, vol. 30, no. 1, pp. 58-61, Jan. 2020, doi: 10.1109/LMWC.2019.2957204

[17]

Chun-Yu Lin, G.-L. Huang, and M.-T. Lin, “Compact ESD protection design for CMOS low-noise amplifier,” IEEE Trans. Electron Devices, vol. 67, no. 1, pp. 33-39, Jan. 2020, doi: 10.1109/TED.2019.2954739

[18]

Chun-Yu Lin and G.-Y. Li, “ESD protection design for open-drain power amplifier in CMOS technology,” IEEE Trans. Device and Materials Reliability, vol. 19, no. 4, pp. 782-790, Dec. 2019, doi: 10.1109/TDMR.2019.2951939

[19]

Chun-Yu Lin and Y.-H. Lai, “π-SCR device for broadband ESD protection in low-voltage CMOS technology,” IEEE Trans. Electron Devices, vol. 66, no. 9, pp. 4107-4110, Sep. 2019, doi: 10.1109/TED.2019.2926813

[20]

J.-T. Chen, Chun-Yu Lin, R.-K. Chang, and M.-D. Ker, “On-chip HBM and HMM ESD protection design for RF applications in 40-nm CMOS process,” IEEE Trans. Electron Devices, vol. 65, no. 12, pp. 5267-5274, Dec. 2018.

[21]

B.-W. Peng and Chun-Yu Lin, “Low-loss I/O pad with ESD protection for K/Ka-bands applications in nanoscale CMOS process,” IEEE Trans. Circuits and Systems II: Express Briefs, vol. 65, no. 10, pp. 1475-1479, Oct. 2018.

[22]

Chun-Yu Lin and C.-Y. Chen, “Low-C ESD protection design with dual resistor-triggered SCRs in CMOS technology,” IEEE Trans. Device and Materials Reliability, vol. 18, no. 2, pp. 197-204, Jun. 2018.

[23]

G.-L. Huang, W.-H. Fu, and Chun-Yu Lin, “Investigation and application of vertical NPN devices for RF ESD protection in BiCMOS technology,” Microelectronics Reliability, vol. 83, pp. 271-280, Apr. 2018.

[24]

Chun-Yu Lin, R.-H. Liu, and M.-D. Ker, “Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process,” Microelectronics Reliability, vol. 78, pp. 258-266, Nov. 2017.

[25]

J.-T. Chen, Chun-Yu Lin, and M.-D. Ker, “On-chip ESD protection device for high-speed I/O applications in CMOS technology,” IEEE Trans. Electron Devices, vol. 64, no. 10, pp. 3979-3985, Oct. 2017.

[26]

Chun-Yu Lin and M.-T. Lin, “Improved stacked-diode ESD protection in nanoscale CMOS technology,” IEICE Electronics Express, vol. 14, no. 13, pp. 20170570, Jul. 2017.

[27]

Chun-Yu Lin and C.-Y. Chen, “Resistor-triggered SCR device for ESD protection in high-speed I/O interface circuits,” IEEE Electron Device Letters, vol. 38, no. 6, pp. 712-715, Jun. 2017.

[28]

Chun-Yu Lin and W.-H. Fu, “Diode string with reduced clamping voltage for efficient on-chip ESD protection,” IEEE Trans. Device and Materials Reliability, vol. 16, no. 4, pp. 688-690, Dec. 2016.

[29]

Chun-Yu Lin, Y.-H. Wu, and M.-D. Ker, “Low-leakage and low-trigger-voltage SCR device for ESD protection in 28-nm high-k metal gate CMOS process,” IEEE Electron Device Letters, vol. 37, no. 11, pp. 1387-1390, Nov. 2016.

[30]

Chun-Yu Lin, Y.-K. Chiu, and S.-Y. Yueh, “Design of local ESD clamp for cross-power-domain interface circuits,” IEICE Electronics Express, vol. 13, no. 20, pp. 20160806, Oct. 2016.

[31]

Chun-Yu Lin and Y.-L. Chiu, “Design of embedded SCR device to improve ESD robustness of stacked-device output driver in low-voltage CMOS technology,” Solid State Electronics, vol. 124, pp. 28-34, Oct. 2016.

[32]

Chun-Yu Lin, P.-H. Wu, and M.-D. Ker, “Area-efficient and low-leakage diode string for on-chip ESD protection,” IEEE Trans. Electron Devices, vol. 63, no. 2, pp. 531-536, Feb. 2016.

[33]

Chun-Yu Lin, P.-H. Chang, and R.-K. Chang, “Impact of inner pickup on ESD robustness of multi-finger MOSFET in 28-nm high-k/metal gate CMOS process,” IEEE Trans. Device and Materials Reliability, vol. 15, no. 4, pp. 633-636, Dec. 2015.

[34]

Chun-Yu Lin and Y.-L. Chiu, “Investigation on SCR-based ESD protection device for biomedical integrated circuits in a 0.18-µm CMOS process,” Microelectronics Reliability, vol. 55, no. 11, pp. 2229-2235, Nov. 2015.

[35]

Chun-Yu Lin and R.-K. Chang, “Design of ESD protection device for K/Ka-band applications in nanoscale CMOS process,” IEEE Trans. Electron Devices, vol. 62, no. 9, pp. 2824-2829, Sep. 2015.

[36]

Chun-Yu Lin, P.-H. Chang, and R.-K. Chang, “Improving ESD robustness of PMOS device with embedded SCR in 28-nm high-k/metal gate CMOS process,” IEEE Trans. Electron Devices, vol. 62, no. 4, pp. 1349-1352, Apr. 2015.

[37]

Chun-Yu Lin and M.-L. Fan, “Design of ESD protection diodes with embedded SCR for differential LNA in a 65-nm CMOS process,” IEEE Trans. Microwave Theory and Techniques, vol. 62, no. 11, pp. 2723-2732, Nov. 2014.

[38]

Chun-Yu Lin and M.-L. Fan, “Optimization on layout style of diode stackup for on-chip ESD protection,” IEEE Trans. Device and Materials Reliability, vol. 14, no. 2, pp. 775-777, Jun. 2014.

[39]

Chun-Yu Lin, Y.-J. Li, and M.-D. Ker, “Design of high-voltage-tolerant stimulus driver with adaptive loading consideration to suppress epileptic seizure in a 0.18-μm CMOS process,” Analog Integrated Circuits and Signal Processing, vol. 79, no. 2, pp. 219-226, May 2014.

[40]

W.-M. Chen, H. Chiueh, T.-J. Chen, C.-L. Ho, C. Jeng, M.-D. Ker, Chun-Yu Lin, Y.-C. Huang, C.-W. Chou, T.-Y. Fan, M.-S. Cheng, Y.-L. Hsin, S.-F. Liang, Y.-L. Wang, F.-Z. Shaw, Y.-H. Huang, C.-H. Yang, and C.-Y. Wu, “A fully integrated 8-channel closed-loop neural-prosthetic CMOS SoC for real-time epileptic seizure control,” IEEE J. Solid-State Circuits, vol. 49, no. 1, pp. 232-247, Jan. 2014.

[41]

Chun-Yu Lin, L.-W. Chu, and M.-D. Ker, “Robust ESD protection design for 40Gb/s transceiver in 65nm CMOS process,” IEEE Trans. Electron Devices, vol. 60, no. 11, pp. 3625-3631, Nov. 2013.

[42]

Chun-Yu Lin, W.-L. Chen, and M.-D. Ker, “Implantable stimulator for epileptic seizure suppression with loading impedance adaptability,” IEEE Trans. Biomedical Circuits and Systems, vol. 7, no. 2, pp. 196-203, Apr. 2013.

[43]

L.-W. Chu, Chun-Yu Lin, and M.-D. Ker, “Design of dual-band ESD protection for 24-/60-GHz millimeter-wave circuits,” IEEE Trans. Device and Materials Reliability, vol. 13, no. 1, pp. 110-118, Mar. 2013.

[44]

Chun-Yu Lin, S.-Y. Tsai, L.-W. Chu, and M.-D. Ker, “Large-swing-tolerant ESD protection circuit for gigahertz power amplifier in a 65-nm CMOS process,” IEEE Trans. Microwave Theory and Techniques, vol. 61, no. 2, pp. 914-921, Feb. 2013.

[45]

Chun-Yu Lin, T.-L. Chang, and M.-D. Ker, “Investigation on CDM ESD events at core circuits in a 65-nm CMOS process,” Microelectronics Reliability, vol. 52, no. 11, pp. 2627-2631, Nov. 2012.

[46]

Chun-Yu Lin, L.-W. Chu, S.-Y. Tsai, and M.-D. Ker, “Design of compact ESD protection circuit for V-band RF applications in a 65-nm CMOS technology,” IEEE Trans. Device and Materials Reliability, vol. 12, no. 3, pp. 554-561, Sep. 2012.

[47]

Chun-Yu Lin, L.-W. Chu, and M.-D. Ker, “ESD protection design for 60-GHz LNA with inductor-triggered SCR in 65-nm CMOS process,” IEEE Trans. Microwave Theory and Techniques, vol. 60, no. 3, pp. 714-723, Mar. 2012.

[48]

M.-D. Ker, Chun-Yu Lin, and W.-L. Chen, “Stimulus driver for epilepsy seizure suppression with adaptive loading impedance,” J. Neural Engineering, vol. 8, no. 6, Dec. 2011.

[49]

Chun-Yu Lin, L.-W. Chu, and M.-D. Ker, “Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process,” Microelectronics Reliability, vol. 51, no. 8, pp. 1315-1324, Aug. 2011.

[50]

M.-D. Ker, Chun-Yu Lin, and Y.-W. Hsiao, “Overview on ESD protection designs of low-parasitic capacitance for RF ICs in CMOS technologies,” IEEE Trans. Device and Materials Reliability, vol. 11, no. 2, pp. 207-218, Jun. 2011.

[51]

M.-D. Ker and Chun-Yu Lin, “High-voltage-tolerant ESD clamp circuit with low standby leakage in nanoscale CMOS process,” IEEE Trans. Electron Devices, vol. 57, no. 7, pp. 1636-1641, Jul. 2010.

[52]

Chun-Yu Lin, M.-D. Ker, and Y.-W. Hsiao, “Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme,” Microelectronics Reliability, vol. 50, no. 6, pp. 831-838, Jun. 2010.

[53]

Chun-Yu Lin, M.-D. Ker, and G.-X. Meng, “Low-capacitance and fast turn-on SCR for RF ESD protection,” IEICE Trans. Electronics, vol. E91-C, no. 8, pp. 1321-1330, Aug. 2008.

[54]

M.-D. Ker and Chun-Yu Lin, “Low-capacitance SCR with waffle layout structure for on-chip ESD protection in RF ICs,” IEEE Trans. Microwave Theory and Techniques, vol. 56, no. 5, pp. 1286-1294, May 2008.