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US Patents
1 W.-M. Wu, Ming-Dou Ker, C.-Y. Lin, and L-.W. Chu, “Integrated circuits including coil circuit and SCR,” US Patent 11,901,353B2, Feb. 13, 2024.
2 Y.-T. Cheng, J.-Y. Hsu, C.-Y. Wu, and Ming-Dou Ker, “Inductive module and device,” US Patent 11,742,697 B1, Aug. 29, 2023.
3 Ming-Dou Ker, Y.-T. Cheng, K.-J. Chen, W.-M. Chen, and C.-Y. Wu, “Wireless charging device,” US Patent 10,978,902B2, Apr. 13, 2021.
4 W.-C. Chen, Ming-Dou Ker, and H.-C. Jiang, “Active surge protection structure and surge-to-digital converter thereof,” US Patent 10,700,517, Jun. 30, 2020.
5 C.-F. Lee, Y.-F. Chou, C.-Y. Wu, Ming-Dou Ker, C.-C. Hung and X.-H. Qian, “Cochlear implant device and stimulating method thereof,” US Patent 10,596,375, Mar. 24, 2020.

6

 Ming-Dou Ker and S.-P. Lin, “Negative high-voltage generation device with multi-stage selection,” US Patent 10,312,791, Jun. 4, 2019.

7

 Ming-Dou Ker and L.-C. Yu, “High-voltage with multi-stage selection in low-voltage transistor process,” US Patent 10,236,770, Mar. 19, 2019.

8

 F. A. Altolaguirre, Ming-Dou Ker, T.-C. Tzeng, and J.-L. Huang, “Electrostatic discharge protection circuit,” US Patent 10,147,717, Dec. 4, 2018.

9

 C.-Y. Lin, J.-T. Chen, Ming-Dou Ker, T.-C. Tzeng, K.-C. Liang, and J.-L. Huang, “Silicon controlled rectifier,” US Patent 10,121,777, Nov. 6, 2018.

10

 Ming-Dou Ker and C.-H. Chuang, “Test method for eliminating electrostatic charges,” US Patent 10,041,995, Aug. 7, 2018.

11

 C.-Y. Lin, Ming-Dou Ker, and W.-T. Wang, “Diode, diode string circuit, and electrostatic discharge protection device having doped region and well isolated from each other,” US Patent 9,997,642, Jun. 12, 2018.

12

 Ming-Dou Ker, W.-L. Wu, J. J.-J. Peng, and R. H.-C. Jiang, “Self-balanced diode device,” US Patent 9,929,151, Mar. 27, 2018.

13

 Ming-Dou Ker and W.-H. Cheng, “Programmable quick discharge circuit and method thereof,” US Patent 9,857,811, Jan. 2, 2018.

14

 Ming-Dou Ker, W.-L. Wu, J. J.-J. Peng, and R. H.-C. Jiang, “Self-balanced diode device,” US Patent 9,786,653, Oct. 10, 2017.

15

 R.-K. Chang, J.-T. Chen, C.-Y. Lin, Ming-Dou Ker, T.-C. Tzeng, and P.-C. Lin, “Electrostatic discharge protection apparatus,” US Patent 9,780,085, Oct. 3, 2017.

16

 C.-Y. Lin, Ming-Dou Ker, and W.-T. Wang, “Gate-bounded silicon controlled rectifier,” US Patent 9,748,220, Aug. 29, 2017.

17

 Ming-Dou Ker, W.-L. Wu, J. J.-J. Peng, and R. H.-C. Jiang, “Self-balanced silicon-controlled rectification device,” US Patent 9,748,219, Aug. 29, 2017.

18

 Ming-Dou Ker, W.-L. Wu, J. J.-J. Peng, and R. H.-C. Jiang, “Bipolar transistor device,” US Patent 9,728,530, Aug. 8, 2017.

19

 K. Nidhi, F. A. Altolaguirre, Ming-Dou Ker, and G.-L. Lin, “Semiconductor device and method for manufacturing the same,” US Patent 9,722,097, Aug. 1, 2017.

20

 M.-Y. Kuo, and Ming-Dou Ker, “Defibrillator device,” US Patent 9,636,513, May 2, 2017.

21

 K. Nidhi, F. A. Altolaguirre, Ming-Dou Ker, and G.-L. Lin, “Cross-domain electrostatic discharge protection device,” US Patent 9,437,591, Sep. 6, 2016.

22

 Ming-Dou Ker and H.-W. Tsai, “Active guard ring structure to improve latch-up immunity,” US Patent 9,425,183, Aug. 23, 2016.

23

 C.-Y. Lin, Ming-Dou Ker, and W.-T. Wang, “Silicon controlled rectifier,” US Patent 9,343,558, May 17, 2016.

24

 Ming-Dou Ker and C.-H. Chuang, “Three-dimension (3D) integrated circuit (IC) package,” US Patent 9,224,702, Dec. 29, 2015.

25

 Ming-Dou Ker, C.-Y. Lin, and C.-T. Wang, “Electrostatic discharge protection circuit,” US Patent 9,190,840, Nov. 17, 2015.

26

 C.-Y. Lin, Ming-Dou Ker, M.-H. Tsai, L.-W. Chu, and M.-H. Song, “Robust ESD protection with silicon-controlled rectifier,” US Patent 9,130,008, Sep. 8, 2015.

27

 P.-T. Liu, L.-W. Chu, and Ming-Dou Ker, “Analog memory cell circuit for the LTPS TFT-LCD,” US Patent 9,111,811, Aug. 18, 2015.

28

 T.-Y. Chen, Ming-Dou Ker, and R. H.-C. Jiang, “Method for fabricating a planar micro-tube discharger structure,” US Patent 9,024,516, May. 5, 2015.

29

 Ming-Dou Ker, C.-C. Yen, T.-Y. Chen, C.-L. Tsai, and S.-F. Chen, “Self-reset transient-to-digital convertor and electronic product utilizing the same,” US Patent 9,001,478, Apr. 7, 2015.

30

 Ming-Dou Ker and C.-Y. Lin, “Electrostatic discharge circuit using inductor-triggered silicon-controlled rectifier,” US Patent 8,952,456, Feb. 10, 2015.

31

 C.-Y. Lin, Y.-J. Li, and Ming-Dou Ker, “Current stimulator,” US Patent 8,892,202, Nov. 18, 2014.

32

 L.-W. Chu, C.-Y. Lin, S.-Y. Tsai, Ming-Dou Ker, M.-H. Tsai, T.-L. Hsu and C.-P. Jou, “ESD protection circuit,” US Patent 8,854,778, Oct. 7, 2014.

33

 Ming-Dou Ker, S.-H. Chen, and K.-H. Lin, “Initial-on SCR device on-chip ESD protection,” US Patent 8,842,400, Sep. 23, 2014.

34

 T.-Y. Chen, Ming-Dou Ker, and R. H.-C. Jiang, “Planar micro-tube discharger structure and method for fabricating the same,” US Patent 8,829,775, Sep. 9, 2014.

35

F. A. Altolaguirre, Ming-Dou Ker, and R. H.-C. Jiang, “Power-rail electro-static discharge (ESD) clamp circuit,” US Patent 8,773,826, Jul. 8, 2014.

36

F.-Y. Tsai, C.-K. Tsai, Y.-H. Peng, and Ming-Dou Ker, “Electrostatic discharge protection apparatus,” US Patent 8,749,931, Jun. 10, 2014.

37

F.-Y. Tsai, Y.-H. Peng, C.-K. Tsai, and Ming-Dou Ker, “ESD protection circuit,” US Patent 8,743,517, Jun. 3, 2014.

38

Ming-Dou Ker, C.-C. Yen, and T.-Y. Chen, “On-chip noise filter circuit,” US Patent 8,649,135, Feb. 11, 2014.

39

Ming-Dou Ker, W.-L. Chen, and C.-Y. Lin, “Load-adaptive bioelectric current simulator,” US Patent 8,527,061, Sep. 3, 2013.

40

Ming-Dou Ker, C.-Y. Lin, and C.-T. Wang, “Electrostatic discharge protection circuit,” US Patent 8,525,265, Sep. 3, 2013.

41

Y.-J. Huang, Y.-N. Jou, Ming-Dou Ker, W.-Y. Chen, C.-W. Hung, and H.-C. Chiou, “Electrostatic discharge protection device,” US Patent 8,507,946, Aug. 13, 2013.

42

F. A. Altolaguirre, Ming-Dou Ker, and C.-C. Wang, “ESD protection circuit,” US Patent 8,498,085, Jul. 30, 2013.

43

C.-Y. Lin, L.-W. Chu, Ming-Dou Ker, M.-H. Tsai, P.-F. Hung, and M.-H. Song, “Electrostatic discharge circuit for radio frequency transmitters,” US Patent 8,493,705, Jul. 23, 2013.

44

W.-T. Hsihe, M.-C. Chou, and Ming-Dou Ker, “ESD protection for high-voltage-tolerance open-drain output pad,” US Patent 8,493,700, Jul. 23, 2013.

45

C.-Y. Lin, Ming-Dou Ker, and F.-Y. Tsai, “High-voltage-tolerant ESD clamp circuit with low leakage current fabricated by low-voltage CMOS process,” US Patent 8,422,180, Apr. 16, 2013.

46

C.-C. Wang, R.-C. Kuo, J.-W. Liu, and Ming-Dou Ker, “Output buffer with process and temperature compensation,” US Patent 8,421,506, Apr. 16, 2013.

47

Ming-Dou Ker, C.-Y. Lin, and C.-T. Wang, “ESD protection circuitry with multi-finger SCRs,” US Patent 8,379,354, Feb. 19, 2013.

48

Ming-Dou Ker and Y.-H. Weng, “Charge pump circuits, systems, and operational methods thereof,” US Patent 8,378,737, Feb. 19, 2013.

49

Y.-D. Shiu, C.-Y. Chang, Ming-Dou Ker, and C.-H. Chuang, “Polydiode structure for photo diode,” US Patent 8,367,457, Feb. 5, 2013.

50

F.-Y. Tsai and Ming-Dou Ker, “Electrostatic discharge circuit for integrated circuit with multiple power domain,” US Patent 8,339,757, Dec. 25, 2012.

51

C.-Y. Lin, L.-W. Chu, Ming-Dou Ker, M.-Hsien Tsai, T.-H. Lu, and P.-F. Hung, “ESD protection for RF circuits,” US Patent 8,279,570, Oct. 2, 2012.

52

Ming-Dou Ker, C.-Y. Lin, and F.-Y. Tsai, “ESD protection circuit with merged triggering mechanism,” US Patent 8,243,404, Aug. 14, 2012.

53

Ming-Dou Ker, S.-C. Chen, and Y.-H. Li, “Gamma voltage conversion device,” US Patent 8,199,091, Jun. 12, 2012.

54

C.-C. Wang, R.-C. Kuo, J.-W. Liu, and Ming-Dou Ker, “Corner detector,” US Patent 8,193,837, Jun. 5, 2012.

55

W.-T. Hsihe, M.-C. Chou, and Ming-Dou Ker, “ESD protection for high-voltage-tolerance open-drain output pad,” US Patent 8,164,870, Apr. 24, 2012.

56

Ming-Dou Ker and Y.-H. Weng, “Charge pump circuits, systems, and operational methods thereof,” US Patent 8,154,333, Apr. 10, 2012.

57

Ming-Dou Ker, J.-J. Peng, and H.-C. Jiang, “ESD protection design with turn-on restraining method and structures,” US Patent RE43,215, Feb. 28, 2012.

Ming-Dou Ker, J.-J. Peng, and H.-C. Jiang, “ESD protection design with turn-on restraining method and structures,” US Patent 6,815,775, Nov. 9, 2004.

58

Ming-Dou Ker, H.-C. Jiang, and W.-Y. Chen, “Transient voltage detection circuit,” US Patent 8,116,049, Feb. 14, 2012.

59

Ming-Dou Ker, S.-H. Chen, and K.-H. Lin, “Initial-on SCR device for on-chip ESD protection,” US Patent 8,102,001, Jan. 24, 2012.

60

Ming-Dou Ker, W.-Y. Chen, and H.-C. Jiang, “System-level ESD detection circuit,” US Patent 8,067,952, Nov. 29, 2011.

61

T.-K. Tseng, C.-H. Chuang, H.-C. Jiang, and Ming-Dou Ker, “Asymmetric bidirectional silicon- controlled rectifier,” US Patent 8,049,247, Nov. 1, 2011.

62

Y.-D. Shiu, C.-Y. Chang, Ming-Dou Ker, and C.-H. Chuang, “Poly diode structure for photo diode,” US Patent 7,993,956, Aug. 9, 2011.

63

Ming-Dou Ker, Y.-W. Hsiao, and H.-C. Jiang, “ESD protection circuit for differential I/O pair,” US Patent 7,974,053, Jul. 5, 2011.

64

B.-S. Huang and Ming-Dou Ker, “Loading reduction device and method,” US Patent 7,974,050, Jul. 5, 2011.

65

C.-H. Chuang and Ming-Dou Ker, “Input stage for mixed-voltage-tolerant buffer with reduced leakage,” US Patent 7,969,190, Jun. 28, 2011.

66

Ming-Dou Ker and C.-Y. Chang, “Substrate-triggered bipolar junction transistor and ESD protection circuit,” US Patent 7,968,906, Jun. 28, 2011.

67

Ming-Dou Ker and C.-Y. Chang, “Substrate-triggered bipolar junction transistor and ESD protection circuit,” US Patent 7,951,681, May 31, 2011.

68

Ming-Dou Ker, Y.-L. Lin, and C.-C. Wang, “2×VDD-tolerant logic circuits and a related 2×VDD- tolerant I/O buffer with PVT compensation,” US Patent 7,932,748, Apr. 26, 2011.

69

Ming-Dou Ker, Y.-L. Lin, and C.-C. Wang, “2×VDD-tolerant logic circuits and a related 2×VDD- tolerant I/O buffer with PVT compensation,” US Patent 7,915,914, Mar. 29, 2011.

70

T.-K. Tseng, C.-H. Chuang, H.-C. Jiang, and Ming-Dou Ker, “Symmetric bidirectional silicon- controlled rectifier,” US Patent 7,915,638, Mar. 29, 2011.

71

Ming-Dou Ker, Y.-W. Hsiao, and H.-C. Jiang, “ESD protection circuit with active triggering,” US Patent 7,889,470, Feb. 15, 2011.

72

Ming-Dou Ker, P.-Y. Chiu, and C. Huang, “ESD detection circuit and related method thereof,” US Patent 7,884,617, Feb. 8, 2011.

73

Ming-Dou Ker, Y.-W. Hsiao, and C.-T. Wang, “Electrostatic discharge protection device and related circuit,” US Patent 7,880,195, Feb. 1, 2011.

74

Ming-Dou Ker, Y.-L. Lin, and C.-C. Wang, “I/O buffer with twice the supply voltage tolerance using normal supply voltage devices,” US Patent 7,868,659, Jan. 11, 2011.

75

S.-H. Chen and Ming-Dou Ker, “ESD protection circuit using self-biased current trigger technique and pumping source mechanism,” US Patent 7,848,068, Dec. 7, 2010.

76

Ming-Dou Ker, S.-H. Chen, and K.-H. Lin, “Initial-on SCR device for on-chip ESD protection,” US Patent 7,825,473, Nov. 2, 2010.

77

Ming-Dou Ker, C.-C. Yen, C.-S. Liao, and T.-Y. Chen, “Transient detection circuit,” US Patent 7,826,187, Nov. 2, 2010.

78

Ming-Dou Ker, C.-H. Chen, and H.-C. Jiang, “Power-rail ESD protection circuit with ultra low gate leakage,” US Patent 7,817,390, Oct. 19, 2010.

79

Ming-Dou Ker, Y.-W. Hsiao, and H.-C. Jiang, “ESD protection circuit for IC with separated power domains,” US Patent 7,817,386, Oct. 19, 2010.

80

Y.-D. Shiu, C.-Y. Chang, Ming-Dou Ker, and C.-H. Chuang, “Polydiode structure for photo diode,” US Patent 7,812,420, Oct. 12, 2010.

81

Ming-Dou Ker, J.-S. Chen, and C.-Y. Hsu, “Current source circuit,” US Patent 7,808,309, Oct. 5, 2010.

82

W.-Y. Chen, H.-C. Jiang, and Ming-Dou Ker, “Bidirectional PNPN silicon-controlled rectifier,” US Patent 7,786,504, Aug. 31, 2010.

83

Ming-Dou Ker, C.-C. Yen, and T.-Y. Chen, “Power-rail ESD protection circuit without lock-on failure,” US Patent 7,764,476, Jul. 27, 2010.

84

Ming-Dou Ker, C.-H. Chen, and H.-C. Jiang, “Power-rail ESD protection circuit with ultra low gate leakage,” US Patent 7,755,871, Jul. 13, 2010.

85

Ming-Dou Ker and C.-K. Deng, “Active device array substrate having electrostatic discharge protection capability,” US Patent 7,738,223, Jun. 15, 2010.

86

Ming-Dou Ker, C.-C. Yen, C.-S. Liao, and T.-Y. Chen, “Transient detection circuit for ESD protection,” US Patent 7,710,696, May 4, 2010.

87

Ming-Dou Ker, J.-H. Chen, and H.-C. Jiang, “Electrostatic discharge protection device and layout thereof,” US Patent 7,705,404, Apr. 27, 2010.

88

Z.-P. Chen and Ming-Dou Ker, “Diode and applications thereof,” US Patent 7,696,580, Apr. 13, 2010.

89

S.-H. Chen and Ming-Dou Ker, “Circuit for electrostatic discharge (ESD) protection,” US Patent 7,692,907, Apr. 6, 2010.

90

Ming-Dou Ker and C.-H. Wu, “Data recovery apparatus and method for reproducing recovery data,” US Patent 7,676,011, Mar. 9, 2010.

91

Ming-Dou Ker, K.-C. Hsu, and H.-C. Jiang, “Electrostatic discharge protection device for mixed voltage interface,” US Patent 7,675,724, Mar. 9, 2010.

92

Ming-Dou Ker, C.-C. Yen, C.-S. Liao, and T.-Y. Chen, “Transient to digital converters,” US Patent 7,675,723, Mar. 9, 2010.

93

Ming-Dou Ker, W.-Y. Chen, and C.-H. Chuang, “High-voltage tolerant power-rail ESD clamp circuit for mixed-voltage I/O interface,” US Patent 7,667,936, Feb. 23, 2010.

94

Ming-Dou Ker, J.-J. Peng, and H.-C. Jiang, “On-chip latch-up protection circuit,” US Patent 7,663,853, Feb. 16, 2010.

95

Ming-Dou Ker, Y.-W. Hsiao, and H.-C. Jiang, “ESD protection circuit with active triggering,” US Patent 7,656,627, Feb. 2, 2010.

96

Ming-Dou Ker, C.-K. Deng, T.-K. Tseng, A. Shih, and S.-C. Yang, "Method of forming ESD protection device with thick poly film,” US Patent 7,632,725, Dec. 15, 2009.

97

Ming-Dou Ker, C.-K. Deng, and W.-T. Sun, “Electrostatic discharge protection structure and electrostatic discharge protection device for a liquid crystal display, and method of making the same,” US Patent 7,626,647, Dec. 1, 2009.

98

C.-T. Wang and Ming-Dou Ker, “ESD detection circuit,” US Patent 7,586,721, Sep. 8, 2009.

99

Ming-Dou Ker, C.-Y. Lin, and C.-T. Wang, “Silicon controlled rectifier,” US Patent 7,582,916, Sep. 1, 2009.

100

Ming-Dou Ker, G.-L. Lin, and H.-C. Hsu, “Devices without current crowding effect at the finger's ends,” US Patent 7,579,658, Aug. 25, 2009.

101

Ming-Dou Ker, H.-T. Liao, and H.-C. Jiang, “High/low voltage tolerant interface circuit and crystal oscillator circuit,” US Patent 7,564,317, Jul. 21, 2009.

102

Ming-Dou Ker, T.-K. Tseng, H.-C. Jiang, C.-Y. Chang, and J.-J. Peng, “Electrostatic discharge protection device and method of manufacturing the same,” US Patent 7,554,159, Jun. 30, 2009.

103

Ming-Dou Ker and K.-H. Lin, “Silicon controlled rectifier for the electrostatic discharge protection,” US Patent 7,542,253, Jun. 2, 2009.

104

Ming-Dou Ker and F.-L. Hu, “Mixed-voltage input/output buffer,” US Patent 7,532,047, May 12, 2009.

105

Ming-Dou Ker and S.-L. Chen, “Mixed voltage input/output buffer having low-voltage design,” US Patent 7,532,034, May 12, 2009.

106

Z.-P. Chen and Ming-Dou Ker, “Diode strings and electrostatic discharge protection circuits,” US Patent 7,525,779, Apr. 28, 2009.

107

Ming-Dou Ker and C.-H. Chuang, “Turn-on-efficient bipolar structures for on-chip ESD protection,” US Patent 7,525,159, Apr. 28, 2009.

108

C.-H. Chuang and Ming-Dou Ker, “Electrostatic discharge protection for power amplifier in radio frequency integrated circuit,” US Patent 7,518,841, Apr. 14, 2009.

109

C.-H. Chuang and Ming-Dou Ker, “Input stage for mixed-voltage-tolerant buffer with reduced leakage,” US Patent 7,504,861, Mar. 17, 2009.
110

Ming-Dou Ker and C.-H. Chuang, “Turn-on-efficient bipolar structures for on-chip ESD protection,” US Patent 7,494,854, Feb. 24, 2009.

111

Ming-Dou Ker, Y.-W. Hsiao, and Y.-K. Tseng, “Bonding pad structure disposed in semiconductor device and related method,” US Patent 7,479,698, Jan. 20, 2009.

112

Y.-D. Shiu, C.-Y. Chang, Ming-Dou Ker, and C.-H. Chuang, “Poly diode structure for photo diode,” US Patent 7,439,597, Oct. 21, 2008.

113

Ming-Dou Ker and K.-C. Hsu, “Electrostatic discharge protection circuit using a double-triggered silicon controlling rectifier,” US Patent 7,436,041, Oct. 14, 2008.

114

Ming-Dou Ker and C.-M. Lee, “ESD protection circuit,” US Patent 7,397,642, Jul. 8, 2008.

115

Ming-Dou Ker, W.-Y. Chen, and C.-H. Chuang, “High-voltage tolerant power-rail ESD clamp circuit for mixed-voltage I/O interface,” US Patent 7,397,280, Jul. 8, 2008.

116

Ming-Dou Ker, K.-C. Hsu, and H.-C. Jiang, “Electrostatic discharge protection device for mixed voltage interface,” US Patent 7,394,630, Jul. 1, 2008.

117

Z.-P. Chen and Ming-Dou Ker, “Diode and applications thereof,” US Patent 7,372,109, May 13, 2008.

118

T.-H. Lai, W.-J. Chang, Ming-Dou Ker, and T.-H. Tang, “Electrostatic discharge protection device and fabrication method thereof,” US Patent 7,368,761, May 6, 2008.

119

Z.-P. Chen, Ming-Dou Ker, and H.-C. Jiang, “ESD protection circuits for mixed-voltage buffers,” US Patent 7,304,827, Dec. 4, 2007.

120

Ming-Dou Ker and C.-M. Lee, “High voltage ESD circuit by using low-voltage device with substrate-trigger and gate-driven technique,” US Patent 7,289,307, Oct. 30, 2007.

121

Ming-Dou Ker, H.-C. Hsu, and W.-Y. Lo, “Method of manufacturing an ESD protection device with the same mask for both LDD and ESD implantation,” US Patent 7,288,449, Oct. 30, 2007.

122

Ming-Dou Ker and W.-Y. Chen, “High-voltage tolerant power rail electrostatic discharge clamp circuit,” US Patent 7,283,342, Oct. 16, 2007.

123

W.-J. Hsu, Ming-Dou Ker, Y.-H. Li, and A. Shih, “Level shifter,” US Patent 7,265,582, Sep. 4, 2007.

124

Ming-Dou Ker and J.-J. Peng, and H.-C. Jiang, “On-chip latch-up protection circuit,” US Patent 7,253,999, Aug. 7, 2007.

125

Ming-Dou Ker and T.-K. Tseng, and H.-C. Jiang, “Charge-device model electrostatic discharge protection using active device for CMOS circuits,” US Patent 7,253,453, Aug. 7, 2007.

126

Ming-Dou Ker and C.-H. Chuang, “Turn-on-efficient bipolar structures with deep N-well for on-chip ESD protection,” US Patent 7,244,992, Jul. 17, 2007.

127

Ming-Dou Ker and C.-M. Lee, “ESD protection unit with ability to enhance trigger-on speed of low voltage triggered PNP,” US Patent 7,242,561, Jul. 10, 2007.

128

Y.-D. Shiu, C.-Y. Chang, Ming-Dou Ker, and C.-H. Chuang, “Polydiode structure for photo diode,” US Patent 7,205,641, Apr. 17, 2007.

129

Ming-Dou Ker,  C.-H. Chuang, and W.-Y. Lo, “Uniform turn-on design on multiple-finger MOSFET for ESD protection application,” US Patent 7,170,726, Jan. 30, 2007.

130

Ming-Dou Ker and C.-S. Tsai, “Charge pump circuit suitable for low-voltage process,” US Patent 7,145,382, Dec. 5, 2006.

131

Ming-Dou Ker, K.-K. Hung, and T.-H. Tang, “Electrostatic discharge protection circuit of non-gated diode and fabrication method thereof,” US Patent 7,141,484, Nov. 28, 2006.

132

Ming-Dou Ker, C.-Y. Chang, and C.-L. Hou, “Automatic transmission line pulse system,” US Patent 7,138,804, Nov. 21, 2006.

133

Ming-Dou Ker, K.-H. Lin, and G.-L. Lin, “Electrostatic discharge protection device,” US Patent 7,129,546, Oct. 31, 2006.

134

Ming-Dou Ker, W.-H. Kung, and Y.-H. Tai, “Level shifter with body-biased circuit,” US Patent 7,123,236, Oct. 17, 2006.
135

S.-C. Yang, A. Shih, Ming-Dou Ker, and T.-K. Tseng, “ESD protection circuit and display panel using the same,” US Patent 7,110,229, Sep. 19, 2006.
136

G.-L. Lin, Y.-N. Jou, and Ming-Dou Ker, “High voltage device with ESD protection,” US Patent 7,098,522, Aug. 29, 2006.
137

Ming-Dou Ker and K.-H. Lin, “ESD protection circuit,” US Patent 7,098,511, Aug. 29, 2006.
138

Ming-Dou Ker, T.-K. Tseng, H.-C. Jiang, and C.-Y. Chang, “Electrostatic discharge protection circuit with active device,” US Patent 7,092,227, Aug. 15, 2006.
139

Ming-Dou Ker and K.-C. Hsu, “Double-triggered silicon controlling rectifier and electrostatic discharge protection circuit thereof,” US Patent 7,071,528, Jul. 4, 2006.
140

Ming-Dou Ker and W.-Y. Lo, “ESD protection circuit with tunable gate-bias,” US Patent 7,064,942, Jun. 20, 2006.
141

Y.-H. Li, S.-C. Yang, A. Shih, Ming-Dou Ker, T.-K. Tseng, and C.-K. Deng, “Method and structure of diode,” US Patent 7,064,418, Jun. 20, 2006.
142

Ming-Dou Ker, H.-C. Hsu, and W.-Y. Lo, “Method of manufacturing an ESD protection device with the same mask for both LDD and ESD implantation,” US Patent 7,049,659, May 23, 2006.
143

S.-L. Chen and Ming-Dou Ker, “Output buffer with low-voltage devices to driver high-voltage signals for PCI-X applications,” US Patent 7,046,036, May 16, 2006.
144

Ming-Dou Ker, W.-H. Kung, and Y.-H. Tai, “TFT with body contacts,” US Patent 7,038,276, May 2, 2006.
145

Ming-Dou Ker, C.-M. Lee, and T.-Y. Chen, “ESD protection designs with parallel LC tank for Giga-Hertz RF integrated circuits,” US Patent 7,023,678, Apr. 4, 2006.
146

Ming-Dou Ker, C.-M. Lee, and T.-Y. Chen, “ESD protection designs with parallel LC tank for Giga-Hertz RF integrated circuits,” US Patent 7,023,677, Apr. 4, 2006.
147

Ming-Dou Ker and W.-Y. Lo, “Low-voltage triggered PNP for ESD protection in mixed voltage I/O interface,” US Patent 7,023,676, Apr. 4, 2006.
148

Ming-Dou Ker, C.-M. Lee, and T.-Y. Chen, “ESD protection design with parallel LC tank for giga-hertz RF integrated circuits,” US Patent 7,009,826, Mar. 7, 2006.
149

Ming-Dou Ker, C.-Y. Chu, and W.-Y. Lo, “Low-voltage curvature-compensated bandgap reference,” US Patent 6,987,416, Jan. 17, 2006.
150

K.-C. Hsu and Ming-Dou Ker, “Power-rail ESD clamp circuit for mixed-voltage I/O buffer,” US Patent 6,954,098, Oct. 11, 2005.
151

Ming-Dou Ker, K.-K. Hung, and T.-H. Tang, “Electrostatic discharge protection circuit of non-gated diode and fabrication method thereof,” US Patent 6,933,573, Aug. 23, 2005.
152

Ming-Dou Ker, C.-S. Tsai, and C.-H. Chuang, “Mixed-voltage CMOS I/O buffer with thin oxide device and dynamic N-well bias circuit,” US Patent 6,927,602, Aug. 9, 2005.
153

Z.-P. Chen, C.-Y. Chang, and Ming-Dou Ker, “ESD protection circuit with whole-chip ESD protection,” US Patent 6,920,026, Jul. 19, 2005.
154

Ming-Dou Ker and M.-L. Wu, “Power-rail ESD clamp circuits with well-triggered PMOS,” US Patent 6,912,109, Jun. 28, 2005.
155

Ming-Dou Ker and C.-H. Chuan, “ESD protection circuit for mixed-voltage I/O ports using substrated triggering,” US Patent 6,903,913, Jun. 7, 2005.
156

Ming-Dou Ker, K.-K. Hung, and T.-H. Tang, “Silicon-on-insulator diodes and ESD protection circuits,” US Patent 6,894,324, May 17, 2005.
157

Ming-Dou Ker, C.-M. Lee, and W.-Y. Lo, “Electrostatic discharge protection device for giga-hertz radio frequency integrated circuits with varactor-LC tanks,” US Patent 6,885,534, Apr. 26, 2005.
158

Ming-Dou Ker, H.-H. Chang, and W.-T. Wang,“CDM ESD protection design using deep N-well structure,” US Patent 6,885,529, Apr. 26, 2005.
159

Ming-Dou Ker, C.-Y. Chu, and W.-Y. Lo, “Low-voltage bandgap reference,” US Patent 6,885,179, Apr. 26, 2005.
160

Ming-Dou Ker, T.-K. Tseng, H.-C. Jiang, C.-Y. Chang, and J.-J. Peng, “Electrostatic discharge protection device and method of manufacturing the same,” US Patent 6,882,009, Apr. 19, 2005.
161

P. Tong, Ming-Dou Ker, and P.-P. Xu, “Stacked-NMOS-triggered SCR device for ESD protection,” US Patent 6,867,957, Mar. 15, 2005.
162

Ming-Dou Ker and K.-H. Lin, “ESD protection circuit,” US Patent 6,867,461, Mar. 15, 2005.
163

Ming-Dou Ker, K.-K. Hung, and T.-H. Tang, “Silicon-on-insulator diodes and ESD protection circuits,” US Patent 6,861,680, Mar. 1, 2005.
164

Ming-Dou Ker and K.-C. Hsu, “ESD protection circuit with high substrate-triggering efficiency,” US Patent 6,858,901, Feb. 22, 2005.
165

Ming-Dou Ker, C.-H. Chuang, K.-C. Lee, and H.-C. Jiang, “Mixed-voltage I/O design with novel floating N-well and gate-tracking circuits,” US Patent 6,838,908, Jan. 4, 2005.
166

Ming-Dou Ker, T.-Y. Chen, and H.-H. Chang, “ESD implantation in deep-submicron CMOS technology for high-voltage-tolerant applications,” US Patent 6,838,734, Jan. 4, 2005.
167

Ming-Dou Ker, C.-Y. Chang, and T.-H. Tang, “Method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process,” US Patent 6,806,160, Oct. 19, 2004.
168

Ming-Dou Ker, K.-K. Hung and S.-C. Chang, “Low-voltage-triggered SOI-SCR device and associated ESD protection circuit,” US Patent 6,768,619, Jul. 27, 2004.
169

Ming-Dou Ker, H.-H. Chang and W.-T. Wang, “SCR devices with deep-N-well structure for on-chip ESD protection circuits,” US Patent 6,765,771, Jul. 20, 2004.
170

Ming-Dou Ker and M.-L. Wu, “Device layout to improve ESD robustness in deep submicron CMOS technology,” US Patent 6,750,517, Jun. 15, 2004.
171

Ming-Dou Ker, K.-K. Hung, and C.-Y. Chang, “SCR devices in silicon-on-insulator CMOS process for on-chip ESD protection,” US Patent 6,750,515, Jun. 15, 2004.
172

Ming-Dou Ker, C.-H. Chung, and H.-C. Jiang, “Electrostatic discharge protection for a mixed-voltage device using a stacked-transistor-triggered silicon controlled rectifier,” US Patent 6,747,861, Jun. 8, 2004.
173

Ming-Dou Ker, K.-K. Hung, and H.-C. Jiang, “Dual-triggered electrostatic discharge protection circuit,” US Patent 6,747,501, Jun. 8, 2004.
174

Ming-Dou Ker, K.-C. Hsu, and W.-Y. Lo, “ESD protection circuit with self-triggered technique,” US Patent 6,744,107, Jun. 1, 2004.
175

P. Tong, Ming-Dou Ker, P.-P. Xu, K.-X. Lin and A. Tam, “Substrate-triggering of ESD-protection device,” US Patent 6,724,592, Apr. 20, 2004.
176

Ming-Dou Ker and H.-C. Jiang, “Low-capacitance bonding pad for semiconductor device,” US Patent 6,717,238, Apr. 6, 2004.
177

Ming-Dou Ker, C.-H. Chuang, and H.-C. Jiang, “ESD Protection Circuit Sustaining High ESD Stress,” US Patent 6,690,067, Feb. 10, 2004.
178

C.-Y. Chang and Ming-Dou Ker, “Substrate-biased silicon diode for electrostatic discharge protection and fabrication method,” US Patent 6,690,065, Feb. 2, 2004.
179

Ming-Dou Ker, W.-Y. Lo, and H.-H. Chang, “Low-leakage diode string for use in the power-rail ESD clamp circuits,” US Patent 6,671,153, Dec. 30, 2003.
180

Ming-Dou Ker, K.-K. Hung, and S.-C. Huang, “Double-triggered electrostatic discharge protection circuit,” US Patent 6,671,147, Dec. 30, 2003.
181

G.-L. Lin and Ming-Dou Ker, “Voltage control component for ESD protection and its relevant circuitry,” US Patent 6,665,160, Dec. 16, 2003.
182

Ming-Dou Ker and Y.-Y. Sung, “Method and apparatus for automatic recovery of microprocessors/microcontrollers during electromagnetic compatibility (EMC) testing,” US Patent 6,658,597, Dec. 2, 2003.
183

Ming-Dou Ker, C.-H. Chuang, and W.-Y. Lo, “ESD protection circuit for mixed-voltage I/O by using stacked NMOS transistors with substrate triggering technique,” US Patent 6,657,835, Dec. 2, 2003.
184

Ming-Dou Ker, K.-K. Hung, and T.-H. Tang, “Silicon-on-insulator diodes and ESD protection circuits,” US Patent 6,653,670, Nov. 25, 2003.
185

Ming-Dou Ker, K.-K. Hung, and T.-H. Tang, “Silicon-on-insulator diodes and ESD protection circuits,” US Patent 6,649,944, Nov. 18, 2003.
186

K.-K. Hung and Ming-Dou Ker, “Semiconductor device with substrate-triggered ESD protection,” US Patent 6,639,283, Oct. 28, 2003.
187

Ming-Dou Ker and H.-C. Jiang, “Low-capacitance bonding pad for semiconductor device,” US Patent 6,633,087, Oct. 14, 2003.
188

C.-Y. Chang, Ming-Dou Ker, and H.-C. Jiang, “Low-noise silicon controlled rectifier for electrostatic discharge protection,” US Patent 6,633,068, Oct. 14, 2003.
189

G.-L. Lin and Ming-Dou Ker, “Two-stage ESD protection circuit with a secondary ESD protection circuit having a quicker trigger-on rate,” US Patent 6,621,673, Sep. 16, 2003.
190

C.-Y. Chang and Ming-Dou Ker, “Low substrate-noise electrostatic discharge protection circuits with bi-directional silicon diodes,” US Patent 6,617,649, Sep. 9, 2003.
191

C.-Y. Chang and Ming-Dou Ker, “Substrate-biased silicon diode for electrostatic discharge protection and fabrication method,” US Patent 6,611,026, Aug. 26, 2003.
192

J.-J. Peng, Ming-Dou Ker, and N.-M. Wang, “Method for improving integrated circuits bonding firmness,” US Patent 6,599,578, Jul. 29, 2003.
193

Ming-Dou Ker, C.-H. Chuang, and G.-L. Lin, “Hybrid diodes with excellent ESD protection capacity,” US Patent 6,590,264, Jul. 8, 2003.
194

C.-Y. Chang, Ming-Dou Ker, and H.-C. Jiang, “Bipolar junction transistors for on-chip electrostatic discharge protection and methods thereof,” US Patent 6,576,974, Jun. 10, 2003.
195

Ming-Dou Ker, H.-H. Chang, and W.-T. Wang, “ESD protection networks with NMOS-bound or PMOS-bound diode structures in a shallow-trench-isolation (STI) CMOS process,” US Patent 6,576,958, Jun. 10, 2003.
196

Ming-Dou Ker, K.-K. Hung, and S.-C. Huang, “Low-voltage-triggered SOI-SCR device and associated ESD protection circuit,” US Patent 6,573,566, Jun. 3, 2003.
197

Ming-Dou Ker, T.-Y. Chen, and H.-H. Chang, “Substrate-triggered technique for on-chip ESD protection circuit,” US Patent 6,566,715, May 20, 2003.
198

G.-L. Lin and Ming-Dou Ker, “ESD protection device for open drain I/O pad in integrated circuits with merged layout structure,” US Patent 6,559,508, May 6, 2003.
199

Ming-Dou Ker, K.-K. Hung, and T.-H. Tang, “Method of forming a silicon controlled rectifier devices in SOI CMOS process for on-chip ESD protection,” US Patent 6,521,952, Feb. 18, 2003.
200

Ming-Dou Ker, T.-Y. Chen, and H.-H. Chang, “ESD implantation method in deep-submicron CMOS technology for high-voltage-tolerant applications with light-doping concentrations,” US Patent 6,514,839, Feb. 4, 2003.
201

Ming-Dou Ker, C.-Y. Chang, and T.-H. Tang, “Lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process,” US Patent 6,498,357, Dec. 24, 2002.
202

Ming-Dou Ker and G.-L. Lin, “Low-voltage-triggered electrostatic discharge protection device and relevant circuitry,” US Patent 6,465,848, Oct. 15, 2002.
203

Ming-Dou Ker, T.-Y. Chen, and T.-H. Tang, “MOS structure with improved substrate-triggered effect for on-chip ESD protection,” US Patent 6,465,768, Oct. 15, 2002.
204

C.-Y. Chang, Ming-Dou Ker, H.-C. Jiang, and J.-J. Peng, “Structure and fabrication method using latch-up implantation for improving latch-up immunity in CMOS fabrication process,” US Patent 6,465,283, Oct. 15, 2002.
205

Ming-Dou Ker and H.-C. Jiang, “Low-capacitance bonding pad for semiconductor device,” US Patent 6,448,641, Sep. 10, 2002.
206

T.-Y. Chen, Ming-Dou Ker, and H.-H. Chang, “Method of fabricating ESD protection device by using the same photolithographic mask for both the ESD implantation and the silicide blocking regions,” US Patent 6,444,404, Sep. 3, 2002.

207

J.-J. Peng, Ming-Dou Ker, and N.-M. Wang, “Method for improving integrated circuits bonding firmness,” US Patent 6,444,295, Sep. 3, 2002.
208

Ming-Dou Ker and C.-Y. Chang, “Charged device model electrostatic discharge protection for integrated circuits,” US Patent 6,437,407, Aug. 20, 2002.
209

G.-L. Lin and Ming-Dou Ker, “Low junction capacitance semiconductor structure and I/O buffer,” US Patent 6,420,774, Jul. 16, 2002.
210

G.-L. Lin and Ming-Dou Ker, “Electrostatic discharge protection circuit with gate-modulated field-oxide device,” US Patent 6,392,860, May 21, 2002.
211

Ming-Dou Ker, C.-C. Wang, and H.-H. Chang, “Gate-coupled ESD protection circuit without transient leakage,” US Patent 6,388,850, May 14, 2002.
212

G.-L. Lin and Ming-Dou Ker, “ESD protection for open drain I/O pad in integrated circuit with parasitic field FET devices,” US Patent 6,355,960, Mar. 12, 2002.
213

Ming-Dou Ker and H.-C. Jiang, “Programmable analog-to-digital converter with programmable non-volatile memory cells,” US Patent 6,335,698, Jan. 1, 2002.
214

G.-L. Lin and Ming-Dou Ker, “Electrostatic discharge device with gate-controlled field oxide transistor,” US Patent 6,316,805, Nov. 13, 2001.
215

G.-L. Lin and Ming-Dou Ker, “CMOS device with deep current path for ESD protection,” US Patent 6,274,911, Aug. 14, 2001.
216

Ming-Dou Ker and H.-H. Chang, “ESD Protection Circuit Without Overstress Gate Driven Effect,” US Patent 6,249,410, Jun. 19, 2001.

217

G.-L. Lin and Ming-Dou Ker, “CMOS device with deep current path for ESD protection,” US Patent 6,169,001, Jan. 2, 2001.
218

Ming-Dou Ker and H.-H. Chang, “ESD bus lines in CMOS IC’s for whole-chip ESD protection,” US Patent 6,144,542, Nov. 7, 2000.
219

Ming-Dou Ker, “ESD protection circuit for mixed mode integrated circuits with separated power pins,” US Patent 6,075,686, Jun. 13, 2000.
220

Ming-Dou Ker, T.-Y. Chen, and C.-Y. Wu, “Substrate-triggering electrostatic discharge protection circuit for deep-submicron integrated circuits,” US Patent 6,072,219, Jun. 6, 2000.
221

G.-L. Lin and Ming-Dou Ker, “Fabrication of ESD protection device using a gate as a silicide blocking mask for a drain region,” US Patent 6,046,087, Apr. 4, 2000.
222

H.-H. Chang, Ming-Dou Ker, K.-T. Lee, and W.-H. Huang, “Output ESD protection using dynamic-floating-gate arrangement,” US Patent 6,034,552, Mar. 7, 2000.
223

Ming-Dou Ker and H.-H. Chang, “Whole-chip ESD protection for CMOS IC’s using bi-directional SCRs,” US Patent 6,011,681, Jan. 4, 2000.
224

Ming-Dou Ker and H.-H. Chang, “CMOS output buffer with CMOS-controlled lateral SCR devices,” US Patent 6,008,684, Dec. 28, 1999.
225

Ming-Dou Ker and H.-H. Chang, “ESD protection scheme for mixed-voltage CMOS integrated circuits,” US Patent 6,002,568, Dec. 14, 1999.
226

Y.-Y. Sung and Ming-Dou Ker, “Reset circuit with transient detection function,” US Patent 5,999,392, Dec. 7, 1999.
227

Ming-Dou Ker and H.-H. Chang, “Cascode LVTSCR and ESD Protection Circuit,” US Patent 5,959,820, Sep. 28, 1999.
228

Ming-Dou Ker, “Output ESD protection with high-current-triggered lateral SCR,” US Patent 5,905,288, May 18, 1999.
229

Ming-Dou Ker, “Charged device mode ESD protection circuit,” US Patent 5,901,022, May 4, 1999.
230

C.-N. Wu and Ming-Dou Ker, “Capacitor-triggered electrostatic discharge protection circuit,” US Patent 5,892,262, Apr. 6, 1999.
231

Ming-Dou Ker, T.-S. Wu, and K.-F. Wang, “N-sided polygonal cell layout for multiple cell transistor,” US Patent 5,852,315, Dec. 22, 1998.
232

Ming-Dou Ker, C.-Y. Wu, C.-C. Huang, C.-N. Wu, and T.-L. Yu “Hexagon CMOS device,” US Patent 5,838,050, Nov. 17, 1998.
233

Ming-Dou Ker, “Output ESD protection with high-current-triggered lateral SCR,” US Patent 5,754,381, May 19, 1998.
234

Ming-Dou Ker and T.-S. Wu, “CMOS output buffer with enhanced high ESD protection capability,” US Patent 5,754,380, May 19, 1998.
235

Ming-Dou Ker, “Area-efficient VDD-to-VSS ESD protection circuit,” US patent 5,744,842, Apr. 28, 1998.
236

C.-N. Wu and Ming-Dou Ker, “Electrostatic discharge protection network,” US Patent 5,721,656, Feb. 24, 1998.
237

Ming-Dou Ker, C.-Y. Wu, C.-C. Huang, M. Wu, and T.-L. Yu, “A close-looped electronic devices,” US Patent 5,714,784, Feb. 3, 1998.
238

C.-N. Wu and Ming-Dou Ker, “Well-couple field-oxide device for ESD protection,” US Patent 5,670,814, Set. 23, 1997.
239

Ming-Dou Ker and T.-S. Wu, “Latchup-free fully-protected CMOS on-chip ESD protection circuit,” US Patent 5,637,900, Jun. 10, 1997.
240

Ming-Dou Ker, C.-Y. Wu, T. Cheng, C.-N. Wu, and T.-L. Yu, “Capacitor-couple ESD protection circuit for submicron CMOS IC,” US Patent 5,631,793, May 20, 1997.
241

Ming-Dou Ker, C.-Y. Wu, H.-H. Chang, C.-Y. Lee, and J. Ko, “Complementary LVTSCR ESD protection circuit for submicron CMOS integrated circuits,” US Patent 5,576,557, Nov. 19, 1996.
242

Ming-Dou Ker and T.-S. Wu, “CMOS on-chip four-LVTSCR ESD protection scheme,” US Patent 5,572,394, Nov. 1996.
243

Ming-Dou Ker, C.-Y. Wu, C.-Y. Lee, and J. Ko, “Complementary-SCR electrostatic discharge protection circuit,” US Patent 5,473,169, Dec. 5, 1995.
244

Ming-Dou Ker, C.-Y. Lee, and C.-Y. Wu, “CMOS on-chip ESD protection circuit and semiconductor structure (part II),” US Patent 5,289,334, Feb. 22, 1994.
245

Ming-Dou Ker, C.-Y. Lee, and C.-Y. Wu, “CMOS on-chip ESD protection circuit and semiconductor structure,” US Patent 5,182,220, Jan. 26, 1993.
246

Ming-Dou Ker, C.-Y. Lee, C.-Y. Wu, and J. Ko, “CMOS ESD protection circuit with parasitic SCR structures,” US Patent 5,140,401, Aug. 18, 1992.