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Local Conference Papers

“A fully integrated 8-channel closed-loop neural-prosthetic CMOS SoC for real-time epileptic seizure control,”

C.-Y. Wu, H. Chiueh, T.-J. Chen, C. Jeng, Ming-Dou Ker, C.-Y. Lin, Y.-C. Huang, C.-W. Chou, T.-Y. Fan, M.-S. Cheng, Y.-L. Hsin, S.-F. Liang, Y.-L. Wang, F.-Z. Shaw, Y.-H. Huang, and W.-M. Chen

Proc. of 2014 VLSI Design/CAD Symposium, Taichung, Taiwan, Aug. 5-8, 2014.

“Whole-chip ESD protection design with SCR for RF applications in 65-nm CMOS process,”

C.-Y. Lin, M.-L Fan, and Ming-Dou Ker

Proc. of 2014 VLSI Design/CAD Symposium, Taichung, Taiwan, Aug. 5-8, 2014.

“三倍VDD電壓共容之輸出緩衝器電路設計與晶片驗證,”

黃俊瑋、柯明道、黃有榕

Proc. of 2013 Electronic Technology Symposium (ETS), Kaohsiung, Taiwan, May 24, 2013.

“On-chip negative high-voltage generator in low-voltage CMOS process for implantable medical applications,”

Y.-C. Huang, C.-Y. Lin, and Ming-Dou Ker

Proc. of 2013 Symposium on Engineering Medicine and Biology Applications (SEMBA), Tainan, Taiwan, Feb. 1-3, 2013.

“Optimization on the embedded SCR to improve ESD robustness of LDMOS devices in 0.25-μm 60-V BCD process,”

Y.-C. Huang and Ming-Dou Ker

Proc. of 2012 International Electron Devices and Materials Symposium, Kaohsiung, Taiwan, Nov. 29-30, 2012, pp. 140-141.

“ESD protection design for 60-GHz applications in a 65-nm CMOS process,”

林群祐、竹立煒、柯明道

Proc. of 2012 Taiwan ESD and Reliability Conference, Hsinchu, Taiwan, Nov. 5-7, 2012.

“應用於兩倍電壓源且具有低漏電流的電源軌線間靜電放電箝制電路,”

葉致廷、柯明道、梁詠智、吳忠霖

Proc. of 2012 Taiwan ESD and Reliability Conference, Hsinchu, Taiwan, Nov. 5-7, 2012.

“Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a HV CMOS process,”

C.-T. Dai, P.-Y. Chiu, Ming-Dou Ker, F.-Y. Tsai, Y.-H. Peng, and C.-K. Tsai

Proc. of 2012 Taiwan ESD and Reliability Conference, Hsinchu, Taiwan, Nov. 5-7, 2012.

“SCR-based ESD protection design for V-band RF applications in a 65-nm CMOS process,”

C.-Y. Lin, L.-W. Chu, and Ming-Dou Ker

Proc. of 2012 Electronic Technology Symposium (ETS), Kaohsiung, Taiwan, Jun. 1, 2012.

“互補式金氧半製程之混合電壓輸出電路設計,”

郭品宏、柯明道、黃有榕

Proc. of 2012 Electronic Technology Symposium (ETS), Kaohsiung, Taiwan, Jun. 1, 2012.

“以改良式電感電容共振腔實現之60-GHz射頻靜電放電防護電路,”

竹立煒、林群祐、蔡翔宇、柯明道、盧澤華、許村來、洪彬舫、宋明相、曾仁洲、張子恒、蔡銘憲

Proc. of 2011 Taiwan ESD and Reliability Conference, Hsinchu, Taiwan, Oct. 31-Nov. 2, 2011, pp. 50-53.

“CDM ESD robustness of 65-nm core circuits with coupling effects,”

Ming-Dou Ker, C.-Y. Lin, and T.-L. Chang

Proc. of 2011 Taiwan ESD and Reliability Conference, Hsinchu, Taiwan, Oct. 31-Nov. 2, 2011, pp. 63-64.

“Investigation on ESD robustness of lateral DMOS in a 0.5-µm 100-V high-voltage BCD SOI process,”

H.-C. Huang and Ming-Dou Ker

Proc. of 2011 Taiwan ESD and Reliability Conference, Hsinchu, Taiwan, Oct. 31-Nov. 2, 2011, pp. 112-115.

“具有可調整維持電壓的電源軌線間靜電放電箝制電路,”

葉致廷、梁詠智、柯明道

Proc. of 2011 Taiwan ESD and Reliability Conference, Hsinchu, Taiwan, Oct. 31-Nov. 2, 2011, pp. 134-137.

“PMOS箝制元件之低漏電靜電放電箝制電路,”

葉致廷、梁詠智、柯明道

Proc. of 2011 Taiwan ESD and Reliability Conference, Hsinchu, Taiwan, Oct. 31-Nov. 2, 2011, pp. 138-141.

“Transient-to-digital converter to detect system-level ESD-induced disturbance in display panel,”

Ming-Dou Ker, W.-Y. Lin, C.-C. Yen, C.-L. Tsai, S.-F. Chen, and T.-Y. Chen

Proc. of 2011 VLSI Design/CAD Symposium, Yunlin, Taiwan, Aug. 2-5, 2011, pp. 296-299.

“Bi-phase stimulus driver with loading adaptability for epileptic seizure suppression,”

Ming-Dou Ker, W.-L. Chen, C.-Y. Lin, and Y.-J. Li

Proc. of 2011 Symposium on Engineering Medicine and Biology Applications (SEMBA), Kaohsiung, Taiwan, Jul. 8-10, 2011.

“Low-leakage power-rail ESD clamp circuit,”

邱柏硯、柯明道

Proc. of 2011 Electronic Technology Symposium (ETS), Kaohsiung, Taiwan, Jun. 10, 2011.

“應用於高頻電路的靜電放電防護二極體之佈局最佳化,”

葉致廷、梁詠智、柯明道

Proc. of 2010 Taiwan ESD and Reliability Conference, Hsinchu, Taiwan, Oct. 25-27, 2010, pp. 54-57.

“應用於系統層級靜電放電防護設計之新式暫態偵測電路,”

林宛彥、顏承正、柯明道、楊哲明、蔡青霖、陳東暘、陳世範

Proc. of 2010 Taiwan ESD and Reliability Conference, Hsinchu, Taiwan, Oct. 25-27, 2010, pp. 42-45.

“55 奈米金氧半製程中使用初始導通技術實作之元件充電模式靜電放電防護設計,”

林群祐、柯明道

Proc. of 2010 Taiwan ESD and Reliability Conference, Hsinchu, Taiwan, Oct. 25-27, 2010, pp. 19-23.

“ESD protection design for 60-GHz RF ICs in nanoscale CMOS technology,”

L.-W. Chu, C.-Y. Lin, Ming-Dou Ker, T.-H. Lu, P.-F. Hung, and H.-C. Li

Proc. of 2010 VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 3-6, 2010, pp. 458-461.

“New ESD transient detection circuit against system-level transient disturbance in TFT LCD panels,”

W.-Y. Lin, C.-C. Yen, Ming-Dou Ker, C.-M. Yang, T.-Y. Chen, and S.-F. Chen

Proc. of 2010 Electronic Technology Symposium (ETS), Kaohsiung, Taiwan, Jun. 18, 2010.

“Design of charge pump circuit with consideration of return-back leakage current,”

H.-W. Tsai, Y.-H. Weng, and Ming-Dou Ker

Proc. of 2010 Electronic Technology Symposium (ETS), Kaohsiung, Taiwan, Jun. 18, 2010.

“BCD高壓製程之PSB和NBL對矽控整流器觸發和持有電壓的影響,”

許哲綸、柯明道、陳穩義、黃曄仁、周業甯、林耿立

Proc. of 2009 Taiwan ESD Conference, Hsinchu, Taiwan, Oct. 26-28, 2009, pp. 27-31.

“應用於過電壓擺幅輸入輸出端靜電防護之雙觸發機制雙向矽控整流器,”

江哲維、陳世宏、柯明道

Proc. of 2009 Taiwan ESD Conference, Hsinchu, Taiwan, Oct. 26-28, 2009, pp. 32-35.

“Design on low-and-constant capacitance with SCR devices for on-chip 5-GHz RF ESD protection,”

C.-Y. Lin and Ming-Dou Ker

Proc. of 2009 Taiwan ESD Conference, Hsinchu, Taiwan, Oct. 26-28, 2009, pp. 53-56.

“65奈米金氧半製程中具低漏電流之靜電防護電路設計,”

王暢資、唐天浩、蘇冠丞、柯明道

Proc. of 2009 Taiwan ESD Conference, Hsinchu, Taiwan, Oct. 26-28, 2009, pp. 57-60.

“提昇多指狀靜電放電保護元件導通均勻度之佈局設計,”

溫詠儒、邱柏硯、柯明道

Proc. of 2009 Taiwan ESD Conference, Hsinchu, Taiwan, Oct. 26-28, 2009, pp. 65-70.

“Impact of gate leakage current on power-rail ESD clamp circuit in nanoscale CMOS technology,”

P.-Y. Chiu and Ming-Dou Ker

Proc. of 2009 Electronic Technology Symposium (ETS), Kaohsiung, Taiwan, Jun. 19, 2009.

“應用於系統層級靜電放電防護設計之暫態對數位轉換器,”

顏承正、柯明道

Proc. of 2008 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 3-5, 2008, pp. 44-47.

“橫向雙擴散電晶體於傳輸線脈波產生系統下之維持電壓量測研究,”

陳穩義、柯明道、黃曄仁、周業甯、林耿立

Proc. of 2008 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 3-5, 2008, pp. 56-59.

“130奈米互補式金氧半製程中具有靜電放電防護功能之差動式低雜訊放大器,”

蕭淵文、柯明道

Proc. of 2008 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 3-5, 2008, pp. 68-71.

“Realization of on-glass bandgap reference circuit with all TFT devices in a 3-µm LTPS process,”

T.-C. Lu, H.-W. Zan, Ming-Dou Ker, C-H Kuo, C.-H. Li, Y.-J. Hsieh, and C.-T. Liu

Proc. of Taiwan Display Conference, Taipei, Taiwan, Jun. 11-12, 2008, pp. 181-184.

“晶片層級元件充電模式與電路板層級元件充電模式靜電放電現象之分析與比較,”

柯明道、蕭淵文

Proc. of 2007 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 5-7, 2007, pp. 21-28.

“高壓積體電路於Latch-up測試下所引發的Snapback現象,”

曾仁洲、陳宥霖、徐中玓、蔡富義、陳柏安、柯明道

Proc. of 2007 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 5-7, 2007, pp. 33-36.

“ESD protection design with low-capacitance requirement for high-speed I/O interfaces in a 130-nm CMOS process,”

Y.-W. Hsiao, C. Huang, Ming-Dou Ker, and Y.-K. Tseng

Proc. of 2007 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 5-7, 2007, pp. 45-48.

“Design of 3xVDD-tolerant power-rail ESD clamp circuit with only 1xVDD low-voltage devices,”

C.-T. Wang, T.-H. Tang, K.-C. Su, and Ming-Dou Ker

Proc. of 2007 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 5-7, 2007, pp. 65-70.

“The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process,”

T.-X. Lai, T.-H. Tang, W.-J. Chang, and Ming-Dou Ker

Proc. of 2007 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 5-7, 2007, pp. 78-83.

“Design on PMOS-triggered SCR devices for on-chip ESD protection in deep-submicron CMOS technology,”

S.-H. Chen, X.-Y. Chang, and Ming-Dou Ker

Proc. of 2007 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 5-7, 2007, pp. 97-101.

“Design and realization of ultra low-capacitance bond pad with inductive compensation for RF circuits in CMOS technology,”

Y.-W. Hsiao, C.-Y. Lin, and Ming-Dou Ker

2007 VLSI Design/CAD Symposium, Taiwan, Aug. 8-10, 2007, pp. 1-4.

“High-voltage-tolerant ESD clamp circuits in low-voltage CMOS technology,”

W.-J. Chang and Ming-Dou Ker

Proc. of 2006 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 6-8, 2006, pp. 17-20.

“A pin latch-up failure and the latch-up trigger current induced NPN snapback effect in high-voltage IC product,”

C.-T. Hsu, I-C. Lin, J.-C. Tseng, Ming-Dou Ker, Y.-L. Chen, F.-Y. Tsai, S.-H. Yu, F.-H. Chen, and P.-A. Chen

Proc. of 2006 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 6-8, 2006, pp. 53-56.

“0.18微米互補式金氧半2.4-GHz功率放大器之靜電放電防護設計,”

徐育達、黃柏獅、梁詠智、柯明道

Proc. of 2006 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 6-8, 2006, pp. 65-68.

“Synchronous bias transmission line pulse system,”

H.-C. Hsu, B.-W. Chang, and Ming-Dou Ker

Proc. of 2006 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 6-8, 2006, pp. 69-72.

“在高壓40伏特金氧半元件之中探討在汲極下端之飄移離子植入對元件之靜電放電防護能力之影響,”

張瑋仁、柯明道、賴泰翔、唐天浩、蘇冠丞

Proc. of 2006 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 6-8, 2006, pp. 73-76.

“機器放電模式靜電放電造成不同電源組間介面電路失效的故障分析,”

江哲維、洪項彬、陳世宏、柯明道

Proc. of 2006 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 6-8, 2006, pp. 77-80.

“On-chip transient detection circuit for system-level ESD protection,”

C.-C. Yen and Ming-Dou Ker

Proc. of 2006 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 6-8, 2006, pp. 94-99.

“Circuit performance degradation of switched-capacitor circuit with bootstrapped switch technique due to gate-oxide overstress in a 130-nm CMOS process,”

J.-S. Chen and Ming-Dou Ker

2006 VLSI Design/CAD Symposium, Taiwan, 2006, Aug. 8-11.

“Design of transient detection circuit for on-chip system-level ESD protection,”

C.-C. Yen, Ming-Dou Ker, and P.-C. Shih

2006 VLSI Design/CAD Symposium, Taiwan, 2006, Aug. 8-11.

“ESD robustness of LTPS N-type TFTs under different layout structures,”

C.-K. Deng, Ming-Dou Ker, J.-Y. Chung, and W.-T. Sun

Proc. of 2006 Taiwan ESD Conference, Taipei, Taiwan, Jun. 15-16, 2006, pp. 235-238.

“Dependencies of device structures and layout parameters on latchup immunity in high-voltage CMOS process,”

S.-F. Hsu, Ming-Dou Ker, G.-L. Lin, and Y.-N. Jou

Proc. of 2005 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 14-16, 2005, pp. 29-31.

“電纜放電測試及其對積體電路可靠度之影響,”

賴泰翔、柯明道

Proc. of 2005 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 14-16, 2005, pp. 58-62.

“A new ESD protection structure with embedded high-voltage P-Type SCR (HVPSCR) for vacuum-fluorescent-display (VFD) driver IC of automotive electronics applications,”

W.-J. Chang and Ming-Dou Ker

Proc. of 2005 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 14-16, 2005, pp. 69-72.

“New matching design in RF low-noise amplifier with low-capacitance ESD protection device,”

B.-S. Huang, Y.-D. Shiu, and Ming-Dou Ker

Proc. of 2005 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 14-16, 2005, pp. 79-82.

“0.18微米互補式金氧半多晶矽P-I-N 二極體之 RF 特性研究與靜電放電防護設計應用,”

徐育達、莊哲豪、柯明道

Proc. of 2005 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 14-16, 2005, pp. 83-88.

“The PMOS-triggered SCR device with initial-on function for effective on-chip ESD protection,”

S.-H. Chen, Ming-Dou Ker, and K.-H. Lin

Proc. of 2005 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 14-16, 2005, pp. 140-143.

“Novel matching technique in ESD-protected low-noise amplifier,”

B.-S. Huang, Y.-D. Shiu, and Ming-Dou Ker

2005 VLSI Design/CAD Symposium, Taiwan, 2005, Aug. 9-12.

“Evaluation on measurement setup for transient-induced latchup in time-domain observation,”

S.-F. Hsu and Ming-Dou Ker

Proc. of 2004 Taiwan ESD Conference, Hsinchu, Taiwan, Oct. 18-20, 2004, pp. 20-24.

“Latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs,”

K.-H. Lin and Ming-Dou Ker

Proc. of 2004 Taiwan ESD Conference, Hsinchu, Taiwan, Oct. 18-20, 2004, pp. 25-30.

“A new failure mechanism of analog I/O cell in 0.18-µm CMOS technology,”

S.-H. Chen, Ming-Dou Ker, C.-H. Chuang, and Z.-P. Chen

Proc. of 2004 Taiwan ESD Conference, Hsinchu, Taiwan, Oct. 18-20, 2004, pp. 58-63.

“Design on diode string to minimize leakage current for ESD protection in 0.18-µm BiCMOS SiGe process,”

W.-L. Wu and Ming-Dou Ker

Proc. of 2004 Taiwan ESD Conference, Hsinchu, Taiwan, Oct. 18-20, 2004, pp. 72-76.

“具有自身基體觸發效能的靜電放電防護電路,”

陳佳惠、柯明道、徐國鈞

Proc. of 2004 Taiwan ESD Conference, Hsinchu, Taiwan, Oct. 18-20, 2004, pp. 77-80.

“ESD protection design for high-speed Stub-Series-Terminated Logic (SSTL) interface application,”

C.-H. Chuang and Ming-Dou Ker

Proc. of 2004 Taiwan ESD Conference, Hsinchu, Taiwan, Oct. 18-20, 2004, pp. 86-89.

“ESD protection design for a 1GHz-10GHz wideband distributed amplifier in CMOS technology,”

Y.-W. Hsiao, B.-J. Kuo, and Ming-Dou Ker

Proc. of 2004 Taiwan ESD Conference, Hsinchu, Taiwan, Oct. 18-20, 2004, pp. 90-94.

“Comparison on ESD robustness of NMOS devices with different salicide-blocking techniques,”

H.-C. Hsu, C.-M. Chen, and Ming-Dou Ker

Proc. of 2004 Taiwan ESD Conference, Hsinchu, Taiwan, Oct. 18-20, 2004, pp. 118-121.

“Reliability study on seal-ring rules in sub-quarter-micron CMOS technology,”

S.-H. Chen, Ming-Dou Ker, and K.-H. Lin

Proc. of 2004 Taiwan ESD Conference, Hsinchu, Taiwan, Oct. 18-20, 2004, pp. 122-125.

“Unify output buffers for both LVDS and RSDS standards,”

Ming-Dou Ker and K.-L. Chuang

2004 VLSI Design/CAD Symposium, Taiwan, Aug. 10-13, 2004.

“Schmitt trigger circuit realized by only thin-gate-oxide devices to receive high-voltage input signals in a 0.13-µm CMOS process,”

S.-L. Chen and Ming-Dou Ker

2004 VLSI Design/CAD Symposium, Taiwan, Aug. 10-13, 2004.

“深次微米金氧半電晶體之通道長度與擴散層金屬接觸點到複晶矽閘極之間距對元件靜電放電耐受度的影響,”

陳東暘、柯明道、唐天浩、黃致遠

Proc. of 2003 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 12-13, 2003, pp. 17-22.

“ESD protection design without over gate-driven effect,”

W.-Y. Chen and Ming-Dou Ker

Proc. of 2003 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 12-13, 2003, pp. 31-35.

“Introduction to the issued ESD patents of Vanguard,”

G.-L. Lin and Ming-Dou Ker

Proc. of 2003 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 12-13, 2003, pp. 40-45.

“ESD related patents of STC/ITRI,”

Ming-Dou Ker, K.-H. Lin, and C.-P. Weng

Proc. of 2003 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 12-13, 2003, pp. 50-55.

“Design on mixed-voltage-tolerant I/O buffer with novel floating N-well and gate-tracking circuits in a 0.13-µm CMOS process,”

C.-H. Chuang and Ming-Dou Ker

Proc. of 2003 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 12-13, 2003, pp. 56-59.

“ESD protection design with low-voltage-triggered PNP device for mixed-voltage I/O interfaces,”

W.-J. Chang, Ming-Dou Ker, and W.-Y. Lo

Proc. of 2003 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 12-13, 2003, pp. 72-76.

“ESD characteristics of native NMOS and its application for on-chip ESD protection in nanoscale CMOS integrated circuits,”

T.-K. Tseng and Ming-Dou Ker

Proc. of 2003 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 12-13, 2003, pp. 103-106.

“On-panel ESD protection design with p-i-n diode in LTPS TFT process,”

S.-C. Yang, Ming-Dou Ker, T.-K. Tseng, C.-K. Deng, A. Shin, and Y.-M. Tsai

Proc. of 2003 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 12-13, 2003, pp. 123-126.

“ESD waveform on N-type low temperature poly-Si TFT devices,”

C.-L. Hou, Ming-Dou Ker, C.-Y. Chang, and F.-T. Chu

Proc. of 2003 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 12-13, 2003, pp. 127-131.

“Difference on the deteriorations of LTPS TFTs caused by TLP zapping in the High/Low ESD current regions,”

C.-K. Deng, Ming-Dou Ker, T.-K. Tseng, S.-C. Yang, and Y.-M. Tasi

Proc. of 2003 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 12-13, 2003, pp. 132-135.

“Double-triggered SCR devices with enhanced turn-on speed for effective on-chip ESD protection,”

K.-C. Hsu and Ming-Dou Ker

Proc. of 2003 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 12-13, 2003, pp. 136-141.

“Whole-chip ESD protection design for IC with power-down application,”

K.-H. Lin and Ming-Dou Ker

Proc. of 2003 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 12-13, 2003, pp. 142-147.

“High-current characteristics of ESD devices in 0.35-μm silicon germanium RF BiCMOS process,”

W.-L. Wu, C.-Y. Chang, and Ming-Dou Ker

Proc. of 2003 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 12-13, 2003, pp. 157-162.

“New distributed ESD protection circuit for broadband RF ICs,”

B.-J. Kuo and Ming-Dou Ker

Proc. of 2003 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 12-13, 2003, pp. 163-168.

“Case study on latchup occurrence in internal circuit of a CMOS IC product,”

S.-H. Chen, Ming-Dou Ker, and C.-P. Weng

Proc. of 2003 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 12-13, 2003, pp. 179-182.

“On-chip ESD protection design with novel dynamic-holding-voltage SCR device for latch-up free,”

Z.-P. Chen and Ming-Dou Ker

Proc. of 2003 Taiwan ESD Conference, Hsinchu, Taiwan, Nov. 12-13, 2003, pp. 183-187.

“Transmitter design for 2Gbps signaling,”

Y.-L. Huang and Ming-Dou Ker

2003 VLSI Design/CAD Symposium, Taiwan, Aug. 12-15, 2003.

“Substrate-triggered ESD clamp circuit for high/low-voltage- tolerant I/O interfaces,”

H.-C. Hsu and Ming-Dou Ker

2003 VLSI Design/CAD Symposium, Taiwan, Aug. 12-15, 2003.

“ESD protection design for mixed-voltage I/O interfaces with input voltage levels higher than VDD and lower than VSS,”

Ming-Dou Ker, W.-J. Chang, and W.-Y. Lo

2003 VLSI Design/CAD Symposium, Taiwan, Aug. 12-15, 2003.

 “On-chip ESD protection design with novel dynamic-holding- voltage SCR,”

Z.-P. Chen and Ming-Dou Ker

2003 VLSI Design/CAD Symposium, Taiwan, Aug. 12-15, 2003.

“Methodology on analog IP reuse for high-speed pipeline A/D converter,”

S.-S. Liu, K.-C. Lee, and Ming-Dou Ker

2003 VLSI Design/CAD Symposium, Taiwan, Aug. 12-15, 2003.

“Internal ESD damage and protection solution for a clock generator IC with multiple separated power pins,”

C.-Y. Chang, Ming-Dou Ker, and Y.-S. Chang

Proc. of 2002 Taiwan EMC Conference, Taipei, Taiwan, Oct. 11-12, 2002, pp. 67-72.

“On-chip ESD protection design to improve machine-model ESD robustness of sub-quarter-micron CMOS integrated circuits,”

H.-C. Hsu and Ming-Dou Ker

Proc. of 2002 Taiwan EMC Conference, Taipei, Taiwan, Oct. 11-12, 2002, pp. 49-54.

“Investigation on ESD robustness of LTPS TFT devices with gate-driven or substrate-triggered bias,”

T.-K. Tseng, Ming-Dou Ker, H.-C. Jiang, and S.-W. Chang

Proc. of 2002 Taiwan ESD Conference, Hsinchu, Taiwan, Sept. 12-13, 2002, pp. 41-44.

“Complementary SCR devices for on-chip ESD protection with substrate-triggered technique,”

K.-C. Hsu and Ming-Dou Ker

Proc. of 2002 Taiwan Electrostatic Discharge Conference, Hsinchu, Taiwan, Sept. 12-13, 2002, pp. 27-32.

“Investigation on ESD robustness of LTPS TFT devices with gate-driven or substrate-triggered bias,”

T.-K. Tseng, Ming-Dou Ker, H.-C. Jiang, and S.-W. Chang

Proc. of 2002 Taiwan Electrostatic Discharge Conference, Hsinchu, Taiwan, Sept. 12-13, 2002, pp. 32-41.

“Investigation on RF performance of diodes for ESD protection in giga-Hz RF circuits,”

C.-M. Lee and Ming-Dou Ker

Proc. of 2002 Taiwan Electrostatic Discharge Conference, Hsinchu, Taiwan, Sept. 12-13, 2002, pp. 45-50.

“Device performance of large scale N-type MOSFET under bond pad,”

J.-J. Peng, Ming-Dou Ker, and H.-C. Jiang

Proc. of 2002 Taiwan Electrostatic Discharge Conference, Hsinchu, Taiwan, Sept. 12-13, 2002, pp. 51-56.

“Chip-level ESD protection circuit-induced latchup failure in a high-voltage CMOS IC product,”

I.-C. Lin, C.-Y. Huang, C.-J. Chao, and Ming-Dou Ker

Proc. of 2002 Taiwan Electrostatic Discharge Conference, Hsinchu, Taiwan, Sept. 12-13, 2002, pp. 66-70.

“Design optimization of ESD protection and latchup prevention for a serial IO IC,”

C.-Y. Huang, W.-F. Chen, S.-Y. Chuan, F.-C. Chiu, J.-C. Tseng, Y.-C. Lin, C.-J. Chao, L.-Y. Leu, and Ming-Dou Ker

Proc. of 2002 Taiwan Electrostatic Discharge Conference, Hsinchu, Taiwan, Sept. 12-13, 2002, pp. 71-76.

“基體觸發技術與閘極驅動技術應用在積體電路靜電放電防護之原理與比較,”

陳東暘、柯明道、蘇金練、唐天浩、陳正剛、簡山傑

Proc. of 2002 Taiwan Electrostatic Discharge Conference, Hsinchu, Taiwan, Sept. 12-13, 2002, pp. 77-82.

“The state-of-art ESD protection design for 900-MHz RF receiver,”

Ming-Dou Ker, C.-M. Lee, C.-P. Chen, and H.-S. Kao

Proc. of 2002 VLSI Design/CAD Symposium, Taiwan, 2002, Aug. 12-15, pp. 59-62.

“Effective ESD protection methodology in sub-quarter-micron CMOS technologies,”

Ming-Dou Ker and H.-C. Jiang

Proc. of the 2001 Taiwan EMC Conference, Taipei, Taiwan, Oct. 2001, pp. 69-74.

“ESD protection design with extra low input capacitance for GHz RF CMOS integrated circuits,”

Ming-Dou Ker and C.-Y. Chang

Proc. of the 2001 Taiwan EMC Conference, Taipei, Taiwan, Oct. 2001, pp. 75-79.

“A case investigation of ESD immunity for high voltage driver IC’s,”

J.-J. Peng, Ming-Dou Ker, and H.-C. Jiang

Proc. of the 2001 Taiwan EMC Conference, Taipei, Taiwan, Oct. 2001, pp. 64-68.

“Design of 8-bit temperature-to-digital converter with error-bit compensation in 0.35-µm CMOS technology,”

Ming-Dou Ker, M.-C. Chien, and T. Lee

2001 VLSI Design/CAD Symposium, Taiwan, 2001, Aug. 14-17.

“Layout design on multi-finger output transistors with ESD protection consideration in a 0.18-µm salicided CMOS process,”

Ming-Dou Ker, C.-H. Chuang, and W.-Y. Lo

2001 VLSI Design/CAD Symposium, Taiwan, 2001, Aug. 14-17.

“ESD protection circuit for CMOS RF integrated circuits without substrate-coupling noise,”

Ming-Dou Ker, H.-C. Jiang, C.-Y. Chang, J.-J. Peng, and T.-K. Tseng

2001 VLSI Design/CAD Symposium, Taiwan, 2001, Aug. 14-17.

“ESD Testing Methods on IC products,”

J.-J. Peng, Ming-Dou Ker, H.-C. Jiang, and C.-Y. Chang

Proc. of the 2000 Taiwan EMC Conference, Taipei, Taiwan, Oct. 12-13, 2000, pp. 344-351.　

“Low-capacitance bond pad for high-speed I/O circuits in CMOS technology,”

Ming-Dou Ker, H.-C. Jiang, and C.-Y. Chang

Proc. of 2000 VLSI Design/CAD Symposium, Taiwan, 2000, Aug. 16-19, pp. 341-344.

“ESD protection design for full-wave bridge rectifying circuit by using poly-silicon diodes in CMOS technology,”

Ming-Dou Ker, T.-Y. Chen, and T.-H. Wang

Proc. of 2000 VLSI Design/CAD Symposium, Taiwan, 2000, Aug. 16-19, pp. 109-112.

“On-chip ESD protection design and verification in a 0.35-mm CMOS ASIC library,”

Ming-Dou Ker, J.-J. Peng, and H.-C. Jiang

Proc. of 1999 Taiwan EMC Conference, Taipei, Taiwan, Oct. 11-12, 1999, pp.65-70.

“Hardware / firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard,”

Ming-Dou Ker and Y.-Y. Sung

Proc. of 1999 Taiwan EMC Conference, Taipei, Taiwan, Oct. 11-12, 1999, pp.76-81.

“The application of transmission-line-pulsing technique on electrostatic discharge protection devices,”

T.-Y. Chen, Ming-Dou Ker, and C.-Y. Wu

Proc. of 1999 Taiwan EMC Conference, Taipei, Taiwan, Oct. 11-12, 1999, pp.260-265.

“VDD-to-VSS ESD Clamp Circuit with Low-Leakage Diode String in a 0.35-µm Silicide CMOS Process,”

Ming-Dou Ker, W.-Y. Lo, and C.-Y. Wu

in Proceeding of the 10th VLSI Design/CAD Symposium, 1999, Aug. 18-21, pp. 217-220.

“Layout verification to improve ESD/latchup reliability in deep-submicron CMOS cell library,”

Ming-Dou Ker and J.-J. Peng

Proc. of 9th VLSI Design/CAD Symposium, Taiwan, Aug. 19-22, 1998, pp. 347-350.

“Design of ESD protection in deep-submicron low-voltage CMOS technology,”

Ming-Dou Ker and C.-Y. Wu

Proc. of the first Chiao-Tung University Tri-Campus Joint Conference, Shanghai/Xian/Hsinchu, China, Sept. 1996, pp.243-283.

“Novel octagon-type layout design for output buffer in deep-submicron low-voltage CMOS VLSI,”

Ming-Dou Ker, K.-F. Wang, and T.-S. Wu

Proc. of 7th VLSI Design/CAD Symposium, Shimen Dam, Taiwan, Aug. 15-17, 1996, pp.279-282.

“On-Chip ESD Protection for CMOS output buffer of deep submicron CMOS VLSI,”

Ming-Dou Ker, K.-F. Wang, M.-C. Joe, and T.-S. Wu

Proc. of 6th VLSI Design/CAD Symposium, Chiayi, Taiwan, Aug. 17-19, 1995, pp.14-17.

“Capacitor-Couple Technique for ESD Protection in Deep Submicron CMOS IC’s,”

Ming-Dou Ker, C.-Y. Wu, T. Cheng, M. Wu, and T.-L. Yu

Proc. of 6th VLSI Design/CAD Symposium, Chiayi, Taiwan, Aug. 17-19, 1995, pp.10-13.

“Whole-chip ESD protection for multiple VDD/VSS CMOS IC’s,”

Ming-Dou Ker, C.-Y. Wu, T. Cheng, H.-J. Tsai, M.-H. Chuang, M. Wu, T.-L. Yu, and A. Wang

Proc. of 5th VLSI Design/CAD Symposium, Tainan, Taiwan, 1994, pp. 132-136.