(PDF)
Tutorial Courses / Invited Talks
Host
Date
Location
Cost-Efficient Methods for Latch-up Prevention in CMOS Integrated Circuits [Ming-Dou Ker]
Challenge on ESD Protection Design for SoC with Separated Power Domains [Ming-Dou Ker]
Advanced ESD Protection Design for CMOS Circuits and Systems [Ming-Dou Ker]
Challenge on ESD Protection Design for SoC with Separated Power Domains [Ming-Dou Ker]
Transient-Induced Latchup in CMOS Integrated Circuits [Ming-Dou Ker]
.jpg){kind=small}
物聯網晶片之先進靜電放電防護技術介紹 (Advanced ESD Protection Techniques for IoT Applications) [Ming-Dou Ker]
Challenge on ESD Protection Design for SoC with Separated Power Domains [Ming-Dou Ker]
ESD Protection Design for Integrated Circuits and Microelectronic Systems [Ming-Dou Ker]
System-Level ESD Protection Design with Transient-to-Digital Converter [Ming-Dou Ker]
Advanced ESD Protection Design in Nanoscale CMOS Integrated Circuits [Ming-Dou Ker]
奇景光電股份有限公司
奇景光電台南總部, 台南樹谷園區, Tainan, Taiwan
Advanced ESD Protection Design in Nanoscale CMOS Integrated Circuits [Ming-Dou Ker]
瑞昱半導體公司
瑞昱半導體新竹總部, 新竹科學園區, Hsinchu, Taiwan
積體電路晶片之靜電放電防護設計 [Ming-Dou Ker]
高雄大學電機系產業人才培訓計畫辦公室
日月光K7廠, 楠梓出口加工區, Kaohsiung, Taiwan
ESD Protection Design in Nanometer CMOS (IEEE Distinguished Lecture) [Ming-Dou Ker]
IEEE Electron Devices Society, Orlando Chapter, USA.
University of Central Florida, USA
IEEE 的實務應用與投稿經驗分享 [Ming-Dou Ker]
IEEE 2013 Taiwan Academic Seminars
交通大學圖書館, Hsinchu, Taiwan
System-Level ESD Protection Design [Ming-Dou Ker]
TSIA (台灣半導體產業協會)
交通大學電子資訊研究大樓, Hsinchu, Taiwan
ESD-Protection Design in Nanometer CMOS [Ming-Dou Ker]
Forum of Mixed-Signal/RF Design and Modeling in Next-Generation CMOS, IEEE International Solid-State Circuits Conference (ISSCC)
San Francisco, CA, USA
ESD and SOA in High-Voltage CMOS Integrated Circuits [Ming-Dou Ker]
經濟部工業局 智慧電子學院
國家晶片系統設計中心, 新竹訓練教室
Design of Ultra-Low-Leakage Power-Rail ESD Clamp Circuits in Nanoscale CMOS Technology [Ming-Dou Ker]
IEEE Electron Devices Society, Chengdu Chapter, China
University of Electronic Science and Technology, Chengdu, China
On-Chip ESD Protection Design for CMOS Integrated Circuits [Ming-Dou Ker]
2012 IEEE International Reliability Physics Symp.
Hyatt Regency, Orange County, Anaheim, CA, USA
New Design Considerations on ESD Clamp Circuit in Nanoscale CMOS Technology (Ming-Dou Ker)
Closed-Loop Epileptic Seizure Detection and Stimulation [Ming-Dou Ker]
The Center for Advanced Medical Engineering and Informatics, Osaka University, Japan
Workshop on Engineering/Information Science for Integrated Life Science and Predictive Medicine, Singapore
Transient‐Induced Latchup (TLU) in CMOS Integrated Circuits [Ming-Dou Ker]
Singapore Institute of Manufacturing Technology (SIMTech)
SIMTech Auditorium, Singapore Institute of Manufacturing Technology, Singapore
Advanced ESD Protection Design in CMOS Integrated Circuits [Ming-Dou Ker]
2011 International Symposium on Integrated Circuits
Singapore
Design of Ultra-Low-Leakage Power-Rail ESD Clamp Circuits in Nanoscale CMOS Technology [Ming-Dou Ker]
TSMC RD & DTP Technical Forum
H-852, FAB12, TSMC
Transient-to-Digital Converter for System-Level ESD Protection Design in CMOS Integrated Circuits (Ming-Dou Ker)
Design of Ultra-Low-Leakage Power-Rail ESD Clamp Circuits in Nanoscale CMOS Technology [Ming-Dou Ker]
積體電路可靠度設計與測試關鍵技術研討會(2011年)
中山大學, 高雄, Taiwan
On-Chip ESD Protection Design for CMOS Integrated Circuits [Ming-Dou Ker]
1st IEEE CASS Summer School in Region 10
中山大學, 高雄, Taiwan
ESD and SOA in High-Voltage CMOS Integrated Circuits [Ming-Dou Ker]
2011 台灣靜電放電防護技術論壇
交通大學電子資訊研究大樓, Hsinchu, Taiwan
積體電路之靜電放電防護設計 (ESD Protection Design in CMOS Integrated Circuits) [Ming-Dou Ker]
交通大學電子系人才培訓中心
交通大學工程四館, Hsinchu, Taiwan
Advanced On-Chip ESD Protection Design in CMOS Integrated Circuits (積體電路晶片之靜電放電防護設計技術) [Ming-Dou Ker]
台灣大學電子工程學研究所
台大博理館401室, Taipei, Taiwan
ESD Protection: System-Level ESD Test vs. Chip-Level ESD Test [Ming-Dou Ker]
聯發科技
聯發科技新竹總部, Hsinchu, Taiwan
ESD and SOA in High-Voltage CMOS Integrated Circuits [Ming-Dou Ker]
交通大學
交通大學交映樓, Hsinchu, Taiwan
積體電路之靜電放電防護設計技術 (Advanced ESD Protection Design in CMOS Integrated Circuits) [Ming-Dou Ker]
台灣科技大學電子工程系
台灣科技大學, Taipei, Taiwan
Transient-to-Digital Converter for System-Level ESD Protection Design [Ming-Dou Ker]
International Symp. on Next-Generation Electronics (ISNE)
Kaohsiung, Taiwan
先进 CMOS 集成电路 ESD 保护设计 (Advanced ESD Protection Design in CMOS Integrated Circuits) [Ming-Dou Ker]
闳康技术检测（上海）有限公司
上海市张江高科技园区 (浦东软件园), China
On-Chip ESD Detection Circuit for System-Level ESD Protection Design [Ming-Dou Ker]
10th International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2010)
Shanghai, China
Measurement of Safe Operating Area (SOA) [Ming-Dou Ker]
Hanwa Electronic Ind. Co., Ltd. (阪和電子)
Wakayama (和歌山), Japan
On-Chip Solution in CMOS Integrated Circuits for System-Level ESD Protection [Ming-Dou Ker]
20th RCJ EOS/ESD/EMC Symposium
Tokyo, Japan
ESD Protection Design for Mixed-Voltage I/O Buffer (混合電壓輸出入界面電路之靜電放電防護設計) [Ming-Dou Ker]
台灣電機電子工程學會
中山大學電資大樓F6019會議室, Kaohsiung, Taiwan
先进 CMOS 集成电路 ESD 保护设计 (Advanced ESD Protection Design in CMOS Integrated Circuits) [Ming-Dou Ker]
重慶大學
中國電子科技集團第二十四研究所, 重慶, China
積體電路封裝測試過程之靜電放電(ESD)案例與晶片上之防護設計及驗證 [Ming-Dou Ker]
2010 先進半導體封裝測試之靜電放電防護技術研討會
義守大學校本部行政大樓國際會議廳, Kaohsiung, Taiwan
Transient-Induced Latchup in CMOS Integrated Circuits [Ming-Dou Ker]
2010 台灣靜電放電防護技術論壇
交通大學電子資訊研究大樓, Hsinchu, Taiwan
Advanced ESD Protection Design in CMOS Integrated Circuits [Ming-Dou Ker]
北京清華大學微電子研究所
北京清華大學東主樓, China
積體電路之靜電放電防護設計 (ESD Protection Design in CMOS Integrated Circuits) [Ming-Dou Ker]
交通大學電子系人才培訓中心
交通大學工程四館, Hsinchu, Taiwan
System-Level Electrostatic Discharge (ESD) Protection in CMOS Integrated Circuits [Ming-Dou Ker]
智原科技公司
智原科技公司, Hsinchu, Taiwan
Transient-Induced Latchup in CMOS Integrated Circuits [Ming-Dou Ker]
清華大學電機工程研究所
清華大學資訊電機館B01演講廳, Hsinchu, Taiwan
Charged-Device-Model (CDM) ESD Protection in CMOS Integrated Circuits [Ming-Dou Ker]
Taiwan Semiconductor Industry Association (TSIA)
交通大學浩然國際會議廳, Hsinchu, Taiwan
積體電路與系統之靜電放電防護設計 ESD Protection in Nanoscale CMOS Integrated Circuits [Ming-Dou Ker]
Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS [Ming-Dou Ker]
2009 IEEE Custom Integrated Circuits Conference (CICC)
DoubleTree Hotel, San Jose, USA
New layout scheme to improve ESD robustness of I/O buffers in fully-silicided CMOS process [Ming-Dou Ker]
2009 Electrical Overstress / Electrostatic Discharge Symposium (EOS/ESD)
Disneyland Hotel, Anaheim, California, USA
CDM ESD Protection in CMOS Integrated Circuits [Ming-Dou Ker]
海思半導體
海思半導體, 深圳市龍崗區阪田華為基地, China
電路板層級元件充電模式之靜電放電測試方法 (Suggestion for Board-Level CDM ESD Test) [Ming-Dou Ker]
[1] On-Chip ESD Protection Design in CMOS Integrated Circuits [Ming-Dou Ker]
[2] ESD Protection Design in High-Voltage Technologies [Ming-Dou Ker and W.-Y. Chen]
(華潤微電子, 無錫)
[1] Transient-Induced Latchup in CMOS Integrated Circuits [IEEE Distinguished Lecturer, Ming-Dou Ker]
[2] On-Chip ESD Protection Design in CMOS Integrated Circuits [IEEE Distinguished Lecturer, Ming-Dou Ker]
(杭州電子科技大學)
ESD Protection Design for CMOS Mixed-Voltage I/O Circuits [Ming-Dou Ker]
電路板層級元件充電模式之靜電放電現象與防護方法 (Board-Level CDM ESD Event) [Ming-Dou Ker]
ESD Protection Design for CMOS Mixed-Voltage I/O Circuits [IEEE Distinguished Lecturer, Ming-Dou Ker]
Mixed-Voltage I/O Circuits and ESD Protection Design in CMOS ICs [Ming-Dou Ker]
ESD Protection Design for CMOS Integrated Circuits [Ming-Dou Ker]
Transient-Induced Latchup in CMOS Integrated Circuits (積體電路之暫態觸發閂鎖效應) [Ming-Dou Ker]
On-Chip ESD Protection Design in CMOS Integrated Circuits [IEEE Distinguished Lecturer, Ming-Dou Ker]
Advanced ESD Protection Design for CMOS Integrated Circuits [Ming-Dou Ker and Elyse Rosenbaum]
[1] Nov. 10-11, 2008
[2] Nov. 12-13, 2008
[3] Nov. 14, 2008
[1]
清華園賓館大會議室
(北京)
[2] 錦江之星張江店大會議室
(上海)
[3] 深圳市南山區科技園科技中二路深圳軟體園4棟6樓教室
On-Chip ESD Protection Design in CMOS Integrated Circuits [IEEE Distinguished Lecturer, Ming-Dou Ker]
Invited Talk:
On-Chip Solution in CMOS Integrated Circuits for
System-Level Electrostatic Discharge (ESD) Protection [Ming-Dou
Ker]
Invited Talk:
Introduction to On-Chip ESD Protection Design in
CMOS Integrated Circuits [Ming-Dou Ker]
International Workshop on Advanced Photonics Failure Analysis Technology in IC (APFA)
Tutorial Course:
System-Level EMC/ESD Issues in CMOS ICs
[Ming-Dou Ker]
Invited Talk:
Introduction to On-Chip ESD Protection Design in
CMOS Integrated Circuits [Ming-Dou Ker]
Tutorial Course:
Advanced ESD (Electrostatic Discharge) Protection
Design in CMOS Integrated Circuits [Ming-Dou Ker]