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Referred Journal Papers

C.-Y. Liang and Ming-Dou Ker,

“Electrostatic discharge protection design with wide bandwidth matching network for radio-frequency integrated circuits,”

in IEEE Transactions on Microwave Theory and Techniques, in press, 2025. (DOI: 10.1109/TMTT.2025.3550381)

C.-Y. Ke and Ming-Dou Ker,

“Improved device structure for electrical safe operating area in SiC 1700-V VDMOSFET,”

Microelectronics Reliability, vol. 169, pp. 1-10, Jun. 2025. (DOI: 10.1016/j.microrel.2025.115749)

H.-C. Lin, Y.-H. Wu, and Ming-Dou Ker,

“Modulation of local field potentials in the deep brain of minipigs through transcranial temporal interference stimulation,”

Neuromodulation, vol. 28, no. 3, pp. 434-443, Apr. 2025.

[Online: https://doi.org/10.1016/j.neurom.2024.10.002]

C.-J. Lai and Ming-Dou Ker,

“Real-time ESD monitoring and control in semiconductor manufacturing environments with silicon chip of ESD event detection,”

in IEEE Journal of the Electron Devices Society, vol. 13, pp. 252-262, Mar. 2025. (DOI: 10.1109/JEDS.2025.354888)

C.-Y. Ke and Ming-Dou Ker,

“Investigation of ESD protection devices for SiC-based monolithic integrated circuits,”

Microelectronics Reliability, vol. 166, pp. 1-10, Mar. 2025. (DOI: 10.1016/j.microrel.2025.115611)

C.-Y. Ke and Ming-Dou Ker,

“Design of GaN-on-silicon power-rail ESD clamp circuit with ultralow leakage current and dynamic timing-voltage detection function,”

IEEE Transactions on Electron Devices, vol. 72, no. 3, pp. 1066-1074, Mar. 2025. (DOI: 10.1109/TED.2025.3529405)

Y.-H. Wu, H.-C. Lin, C.-W. Huang, C.-Y. Wu, and Ming-Dou Ker,

“Stimulation-induced artifact removal of the local field potential through hardware design: toward the implantable closed-loop deep brain stimulation,”

in IEEE Access, vol. 12, pp. 171488-171499, Nov. 2024. (DOI: 10.1109/ACCESS.2024.3498053)

W.-C. Wang and Ming-Dou Ker,

“Fully integrated GaN-on-Silicon power-rail ESD clamp circuit without transient leakage current during normal power-on operation,”

in IEEE Journal of the Electron Devices Society, vol. 12, pp. 760-769, Sept. 2024. (DOI: 10.1109/JEDS.2024.3462590)

C.-Y. Wu, C.-W. Huang, Y.-W. Chen, C.-K. Lai, C.-C. Hung, and Ming-Dou Ker,

“Design of CMOS analog front-end local-field potential chopper amplifier with stimulation artifact tolerance for real-time closed-loop deep brain stimulation SoC applications,”

in IEEE Transactions on Biomedical Circuits and Systems, vol. 18, no. 3, pp. 539-551, June 2024. (DOI: 10.1109/TBCAS.2024.3352414)

C.-Y. Ke and Ming-Dou Ker, 

“Latchup risk in a 4H-SiC process,” 

in IEEE Transactions on Electron Devices, vol. 71, no. 5, pp. 3424-3428, May 2024. (DOI: 10.1109/TED.2024.3372489)

C.-Y. Ke and Ming-Dou Ker, 

“Investigation of safe operating area and behavior of unclamped inductive switching on 4H-SiC VDMOSFET,” 

Microelectronics Reliability, vol. 155, pp. 1-9, Apr. 2024. (DOI: 10.1016/j.microrel.2024.115347)

C.-W. Hsu and Ming-Dou Ker, 

“Cost-efficient solution to overcome latch-up path in 5 V-tolerant I/O with low-voltage biased NBL isolation ring in a 0.18-μm BCD technology,” 

in IEEE Transactions on Electron Devices, vol. 71, no. 3, pp. 2224-2227, Mar. 2024. (DOI: 10.1109/TED.2024.3350002)

C.-W. Hsu and Ming-Dou Ker, 

“Design of bi-directional ESD protection circuit with uni-directional ESD device in BCD technology,” 

in IEEE Transactions on Electron Devices, vol. 70, no. 10, pp. 5028-5035, Oct. 2023. (DOI: 10.1109/TED.2023.3307653)

W.-M. Wu, S.-H. Chen, C.-A. Shih, B. Parvais, N. Collaert, Ming-Dou Ker, T.-L. Wu, and G. Groeseneken,

"ON-state human body model ESD failure mechanisms in GaN-on-Si RF MIS-HEMTs,"

in IEEE Electron Device Letters, vol. 44, no. 8, pp. 1248-1251, Aug. 2023. (DOI: 10.1109/LED.2023.3290034)

C.-W. Huang, C.-K. Lai, C.-C. Hung, C.-Y. Wu, and Ming-Dou Ker,

“A CMOS synchronized sample-and-hold artifact blanking analog front-end local field potential acquisition unit with ± 3.6-V stimulation artifact tolerance and monopolar electrode-tissue impedance measurement circuit for closed-loop deep brain stimulation SoCs,”

in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 6, pp. 2257-2270, June 2023. (DOI: 10.1109/TCSI.2023.3254891)

C.-C. Hsieh, Y.-H. Wu, and Ming-Dou Ker,

"Design of dual-configuration dual-mode stimulator in low-voltage CMOS process for neuro-modulation,"

in IEEE Trans. on Biomedical Circuits and Systems, vol. 17, no. 2, pp. 273-285, Apr. 2023. (DOI: 10.1109/TBCAS.2023.3246164)

Ming-Dou Ker and Z.-H. Jiang,

 “Overview on latch-up prevention in CMOS integrated circuits by circuit solutions,”

in IEEE Journal of the Electron Devices Society, vol. 11, pp. 141-152, Feb. 2023. (DOI: 10.1109/JEDS.2022.3228859)

Y.-C. Huang and Ming-Dou Ker,

“Investigation on CDM ESD protection capability among power-rail ESD clamp circuits in CMOS ICs with decoupling capacitors,” 

IEEE Journal of the Electron Devices Society, vol. 11, pp. 84-94, 2023. (DOI: 10.1109/JEDS.2022.3228859)

H.-C. Lin, Y.-H. Wu, C.-W. Huang, and Ming-Dou Ker, 

“Verification of the beta oscillations in the subthalamic nucleus of the MPTP-induced parkinsonian minipig model,” 

Brain Research, vol. 1798, pp. 148165-1 ~ 148165-8, Jan. 2023. (DOI: 10.1016/j.brainres.2022.148165)

[Online: https://doi.org/10.1016/j.brainres.2022.148165]

“System-level ESD-induced voltage fluctuation to the power of integrated circuits on system board,” 

IEEE Trans. on Electromagnetic Compatibility, vol. 64, no. 6, pp. 1883-1889, Dec. 2022. (DOI: 10.1109/TEMC.2022.3220651)

Z.-H. Jiang and Ming-Dou Ker,

“Latch-up prevention with auto-detector circuit to stop latch-up occurrence in CMOS integrated circuits,”

IEEE Transactions on Electromagnetic Compatibility, vol. 64, no. 6, pp. 1785-1792, Dec. 2022. (DOI: 10.1109/TEMC.2022.3202806)

I.-H. Wu and Ming-Dou Ker,

“ESD-event detector for ESD control applications in semiconductor manufacturing factories,”

IEEE Transactions on Electromagnetic Compatibility, vol. 64, no. 6, pp. 1793-1801, Dec. 2022. (DOI: 10.1109/TEMC.2022.3195233)

C.-W. Hsu, Y.-H. Li, and Ming-Dou Ker,

“Optimization on bi-directional PNP ESD protection device for high-voltage FlexRay applications,”

IEEE Transactions on Electron Devices, vol. 69, no. 10, pp. 5713-5721, Oct. 2022. (DOI: 10.1109/TED.2022.3198388)

Z.-H. Jiang and Ming-Dou Ker,

“Schottky-embedded isolation ring to improve latch-up immunity between HV and LV circuits in a 0.18 μm BCD technology,”

IEEE Journal of the Electron Devices Society, vol. 10, pp. 516-524, Jul. 2022. (DOI: 10.1109/JEDS.2022.3188938)

Z.-H. Jiang and Ming-Dou Ker,

“The parasitic latch-up path from substrate P+ guard ring to the NMOS in deep N-Well operating with negative voltage sources,”

IEEE Electron Device Letters, vol. 43, no. 4, pp. 604-606, Apr. 2022. (DOI: 10.1109/LED.2022.3155480)

W.-M. Wu, Ming-Dou Ker, S.-H. Chen, A. Sibaja-Hernandez, S. Yadav, U. Peralagu, H. Yu, A. Alian, V. Putcha, B. Parvais, N. Collaert, and G. Groeseneken,

“ESD HBM discharge model in RF GaN-on-Si (MIS)HEMTs,”

IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 2180-2187, Apr. 2022. (DOI: 10.1109/TED.2022.3141038)

Y.-C. Huang and Ming-Dou Ker,

“Study on CDM ESD robustness among on-chip decoupling capacitors in CMOS integrated circuits,”

IEEE Journal of the Electron Devices Society, vol. 9, pp. 881-890, Oct. 2021. (DOI: 10.1109/JEDS.2021.3116961)

S.-H. Wang, Y.-K. Huang, C.-Y. Chen, L.-Y. Tang, Y.-F. Tu, P.-C. Chang, C.-F. Lee, C.-H. Yang, C.-C. Hung, C.-H. Liu, Ming-Dou Ker, and C.-Y. Wu,

“Design of a bone-guided cochlear implant microsystem with monopolar biphasic multiple stimulations and evoked compound action potential acquisition and its in-vivo verification,”

IEEE Journal of Solid-State Circuits, vol. 56, no. 10, pp. 3062-3076, Oct. 2021. (DOI: 10.1109/JSSC.2021.3087629)

C.-C. Hsieh and Ming-Dou Ker,

“Monopolar biphasic stimulator with discharge function and negative level shifter for neuromodulation SoC integration in low-voltage CMOS process,”

IEEE Trans. on Biomedical Circuits and Systems, vol. 15, no. 3, pp. 568-579, Jun. 2021. (DOI: 10.1109/TBCAS.2021.3087036)

C.-Y. Wu and Ming-Dou Ker,

“From bioelectronics to nanobioelectronics: the biomedical electronics translational research center,”

in IEEE Nanotechnology Magazine, vol. 15, no. 4, pp. 3-6, Aug. 2021. (DOI: 10.1109/MNANO.2021.3081786)

Y.-S. Shen and Ming-Dou Ker,

“The impact of holding voltage of transient voltage suppressor (TVS) on signal integrity of microelectronics system with CMOS ICs under system-level ESD and EFT/burst tests,”

IEEE Transactions on Electron Devices, vol. 68, no. 5, pp. 2152-2159, May. 2021. (DOI: 10.1109/TED.2021.3063208)

C.-Y. Hsueh and Ming-Dou Ker,

“Stacking-MOS protection design for interface circuits against cross-domain CDM ESD stresses,”

IEEE Transactions on Electron Devices, vol. 68, no. 4, pp. 1461-1470, Apr. 2021. (DOI: 10.1109/TED.2021.3061325)

R.-K. Chang, B.-W. Peng, and Ming-Dou Ker,

“Schottky-embedded silicon-controlled rectifier with high holding voltage realized in a 0.18-μm low-voltage CMOS process,”

IEEE Transactions on Electron Devices, vol. 68, no. 4, pp. 1764-1771, Apr. 2021. (DOI: 10.1109/TED.2021.3059193)

R.-K. Chang and Ming-Dou Ker,

“Using schottky barrier diode to improve latch-up immunity for CMOS ICs operating with negative voltage sources,”

IEEE Electron Device Letters, vol. 42, no. 3, pp. 395-397, Mar. 2021. (DOI: 10.1109/LED.2021.3055212)

S.-P. Lin and Ming-Dou Ker,

“Design of stage-selective negative voltage generator to improve on-chip power conversion efficiency for neuron stimulation,”

IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 67, no. 11, pp. 4122-4131, Nov. 2020. (DOI: 10.1109/TCSI.2020.3012086)

T.-Y. Yen and Ming-Dou Ker,

“Design of dual-mode stimulus chip with built-in high voltage generator for biomedical applications,”

IEEE Trans. on Biomedical Circuits and Systems, vol. 14, no. 5, pp. 961-970, Oct. 2020. (DOI: 10.1109/TBCAS.2020.2999398)

W.-M. Wu, Ming-Dou Ker, S.-H. Chen, J.-T. Chen, D. Linten, and G. Groeseneken,

“RF/high-speed I/O ESD protection: co-optimizing strategy between BEOL capacitance and HBM immunity in advanced CMOS process,”

IEEE Trans. on Electron Devices, vol. 67, no. 7, pp. 2752-2759, Jul. 2020. (DOI: 10.1109/TED.2020.2994492)

C.-Y. Ke and Ming-Dou Ker,

“On-chip over-voltage protection design against surge events on the CC pin of USB type-C interface,”

IEEE Trans. on Electron Devices, vol. 67, no. 7, pp. 2702-2709, Jul. 2020. (DOI: 10.1109/TED.2020.2992383)

R.-K. Chang, C.-Y. Lin, and Ming-Dou Ker,

“Design of fin-diode-triggered rotated silicon-controlled rectifier for high-speed digital application in 16-nm FinFET process,”

IEEE Trans. on Electron Devices, vol. 67, no. 7, pp. 2725-2731, Jul. 2020. (DOI: 10.1109/TED.2020.2995145)

K. Nidhi, J.-H. Lee, S.-C. Huang, and Ming-Dou Ker,

“Energy transformation between the inductor and the power transistor for the unclamped inductive switching (UIS) test,”

IEEE Trans. on Device and Materials Reliability, vol. 20, no. 2, pp. 413-419, Jun. 2020. (DOI: 10.1109/TDMR.2020.2985306)

R.-K. Chang and Ming-Dou Ker,

“Design of high-voltage-tolerant power-rail ESD protection circuit for power pin of negative voltage in low-voltage CMOS processes,”

IEEE Trans. on Electron Devices, vol. 67, no. 1, pp. 40-46, Jan. 2020. (DOI: 10.1109/TED.2019.2954754)

X.-H. Qian, Y.-C. Wu, T.-Y. Yang, C.-H. Cheng, H.-C. Chu, W.-H. Cheng, T.-Y. Yen, T.-H. Lin, Y.-J. Lin, Y.-C. Lee, J.-H. Chang, S.-T. Lin, S.-H. Li, T.-C. Wu, C.-C. Huang, S.-H. Wang, C.-F. Lee, C.-H. Yang, C.-C. Hung, T.-S. Chi, C.-H. Liu, Ming-Dou Ker, and C.-Y. Wu,

“Design and in-vivo verification of a CMOS bone-guided cochlear implant microsystem,”

IEEE Trans. on Biomedical Engineering, vol. 66, no. 11, pp. 3156-3167, Nov. 2019. (DOI: 10.1109/TBME.2019.2901374)

Z. Luo, L.-C. Yu, and Ming-Dou Ker,

“An efficient, wide-output, high-voltage charge pump with a stage selection circuit realized in a low-voltage CMOS process,”

IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 66, no. 9, pp. 3437-3444, Sep. 2019. (DOI: 10.1109/TCSI.2019.2924581)

K. Nidhi, Ming-Dou Ker, J.-H. Lee, and S.-C. Huang,

“Avalanche ruggedness capability and improvement of 5-V n-channel large-array MOSFET in BCD process,”

IEEE Trans. on Electron Devices, vol. 66, no. 7, pp. 3040-3048, Jul. 2019. (DOI: 10.1109/TED.2019.2916032)

C.-C. Chen and Ming-Dou Ker,

“Study and verification on the latch-up path between I/O pMOS and N-type decoupling capacitors in 0.18-μm CMOS technology,”

IEEE Trans. on Device and Materials Reliability, vol. 19, no. 2, pp. 445-451, Jun. 2019. (DOI: 10.1109/TDMR.2019.2916721)

J.-T. Chen and Ming-Dou Ker,

“ESD protection design with diode-triggered quad-SCR for separated power domains,”

IEEE Trans. on Device and Materials Reliability, vol. 19, no. 2, pp. 283-289, Jun. 2019. (DOI: 10.1109/TDMR.2019.2903209)

W.-C. Chen and Ming-Dou Ker,

“Area-efficient on-chip transient detection circuit for system-level ESD protection against transient-induced malfunction,”

IEEE Trans. on Device and Materials Reliability, vol. 19, no. 2, pp. 363-369, Jun. 2019. (DOI: 10.1109/TDMR.2019.2910351)

C.-W. Liu, Y.-L. Chen, P.-C. Liao, S.-P. Lin, T.-W. Wang, M.-J. Chung, P.-H. Chen, Ming-Dou Ker, and C.-Y. Wu,

“An 82.9%-efficiency triple-output battery management unit for implantable neuron stimulator in 180-nm standard CMOS,”

IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 66, no. 5, pp. 788-792, May. 2019. (DOI: 10.1109/TCSII.2019.2909813)

“Optimization design on active guard ring to improve latch-up immunity of CMOS integrated circuit,”

C.-C. Chen and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 66, no. 4, pp. 1648-1655, Apr. 2019. (SCI, EI)

“On-chip HBM and HMM ESD protection design for RF applications in 40-nm CMOS process,”

J.-T. Chen, C.-Y. Lin, R.-K. Chang, and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 65, no. 12, pp. 5267-5274, Dec. 2018. (SCI, EI)

“A fully integrated 16-channel closed-loop neural prosthetic CMOS SoC with wireless power and bidirectional data telemetry for real-time efficient human epileptic seizure control,”

C.-H. Cheng, P.-Y. Tsai, T.-Y. Yang, W.-H. Cheng, T.-Y. Yen, Z.g Luo, X.-H. Qian, Z.-X. Chen, T.-H. Lin, W.-H. Chen, W.-M. Chen, S.-F. Liang, F.-Z. Shaw, C.-S. Chang, F.-Y. Shih, Y.-L. Hsin, C.-Y. Lee,  Ming-Dou Ker, and C.-Y. Wu

IEEE Journal of  Solid-State Circuits, vol. 53, no. 11, pp. 3314-3326, Nov. 2018.

“Improving safe-operating-area of a 5-V n-channel large array MOSFET in a 0.15-μm BCD process,”

K. Nidhi, Ming-Dou Ker, T. Lin, and J.-H. Lee

IEEE Trans. on Electron Devices, vol. 65, no. 7, pp. 2948-2956, Jul. 2018. (SCI, EI)

“A high-voltage-tolerant and power-efficient stimulator with adaptive power supply realized in low-voltage CMOS process for implantable biomedical applications,”

Z. Luo and Ming-Dou Ker

IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 8, no. 2, pp. 178-186, Jun. 2018. (SCI, EI)

“Self-reset transient detection circuit for on-chip protection against system-level electrical-transient disturbance,”

X.-R. Kang and Ming-Dou Ker

IEEE Trans. on Device and Materials Reliability, vol. 18, no. 1, pp. 114-121, Mar. 2018. (SCI, EI)

“Design of power-rail ESD clamp with dynamic timing-voltage detection against false trigger during fast power-on events,”

J.-T. Chen and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 65, no. 3, pp. 838-846, Mar. 2018. (SCI, EI)

“Comparison between high-holding-voltage SCR and stacked low-voltage devices for ESD protection in high-voltage applications,”

C.-T. Dai and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 65, no. 2, pp. 798-802, Feb. 2018. (SCI, EI)

“Validation of a fully integrated closed-loop neuromodulation SoC with wireless power and bidirectional data telemetry for real-time seizure control: preliminary results from swine model,”

Y.-L. Hsin, C. Cheng-Siu, S. Fu-Yuan, C.-H. Cheng, Ming-Dou Ker, and C.-Y. Wu

Journal of the Neurological Sciences, vol. 381, pp. 343, Oct. 2017. (SCI, EI)

“A digitally dynamic power supply technique for 16-channel 12 V-tolerant stimulator realized in a 0.18-μm 1.8-V/3.3-V low-voltage CMOS process,”

Z. Luo, Ming-Dou Ker, T.-Y. Yang, and W.-H. Cheng

IEEE Trans. on Biomedical Circuits and Systems, vol. 11, no. 5, pp. 1087-1096, Oct. 2017. (SCI, EI)

“On-chip ESD protection device for high-speed I/O applications in CMOS technology,”

J.-T. Chen, C.-Y. Lin, and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 64, no. 10, pp. 3979-3985, Oct. 2017. (SCI, EI)

“System-level ESD protection for automotive electronics by co-design of TVS and CAN transceiver chips,”

C.-H. Chuang and Ming-Dou Ker

IEEE Trans. on Device and Materials Reliability, vol. 17, no. 3, pp. 570-576, Sep. 2017. (SCI, EI)

“An ultra-low voltage CMOS voltage controlled oscillator with process and temperature compensation,”

T.-C. Lu, Ming-Dou Ker, and H.-W. Zan

IEICE Trans. Electron., vol. E100-C, no. 8, pp. 675-683, Aug. 2017. (SCI, EI)

“Investigation of unexpected latchup path between HV-LDMOS and LV-CMOS in a 0.25-μm 60-V/5-V BCD technology,”

C.-T. Dai and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 64, no. 8, pp. 3519-3523, Aug. 2017. (SCI, EI)

“A CMOS-process-compatible low-voltage junction-FET with adjustable pinch-off voltage,”

K. Nidhi and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 64, no. 7, pp. 2812-2819, Jul. 2017. (SCI, EI)

“Regulated charge pump with new clocking scheme for smoothing the charging current in low voltage CMOS process,”

Z. Luo, Ming-Dou Ker, W.-H. Cheng, and T.-Y. Yen

IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 64, no. 3, pp. 528-536, Mar. 2017. (SCI, EI)

“ESD protection design for touch panel control IC against latchup-like failure induced by system-level ESD test,”

Ming-Dou Ker, P.-Y. Chiu, W.-T. Shieh, and C.-C. Wang

IEEE Trans. on Electron Devices, vol. 64, no. 2, pp. 642-645, Feb. 2017. (SCI, EI)

“A 8 phases 192 MHz crystal-less clock generator with PVT calibration,”

T.-C. Lu, Ming-Dou Ker, H.-W. Zan, J.-C. Liu, and Y. Lee

IEICE Trans. on Fundamentals of Electrons, Communications and Computer Sciences, vol. E100-A, no. 1, pp. 275-282, Jan. 2017. (SCI, EI)

“A high-voltage-tolerant and precise charge-balanced neuro-stimulator in low voltage CMOS process,”

Z. Luo and Ming-Dou Ker

IEEE Trans. on Biomedical Circuits and Systems, vol. 10, no. 6, pp. 1087-1099, Dec. 2016. (SCI, EI)

“Low-leakage bidirectional SCR with symmetrical trigger circuit for ESD protection in 40-nm CMOS process,”

F. A. Altolaguirre and Ming-Dou Ker

IEEE Trans. on Device and Materials Reliability, vol. 16, no. 4, pp. 549-555, Dec. 2016. (SCI, EI)

“Low-leakage and low-trigger-voltage SCR device fo ESD protection in 28-nm high-k metal gate CMOS process,”

C.-Y. Lin, Y.-H. Wu, and Ming-Dou Ker

IEEE Electron Device Letters, vol. 37, no. 11, pp. 1387-1390, Nov. 2016. (SCI, EI)

“Investigation of human-body-model and machine-model ESD robustness on stacked low-voltage field-oxide devices for high-voltage applications,”

Y.-J. Huang and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 63, no. 8, pp. 3193-3198, Aug. 2016. (SCI, EI)

“Quad-SCR device for cross-domain ESD protection,”

F. A. Altolaguirre and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 63, no. 8, pp. 3177-3184, Aug. 2016. (SCI, EI)

“Optimization of guard ring structures to improve latchup immunity in an 18 V DDDMOS process,”

C.-T. Dai and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 63, no. 6, pp. 2449-2454, Jun. 2016. (SCI, EI)

“ESD protection design with stacked high-holding-voltage SCR for high-voltage pins in a battery-monitoring IC,”

C.-T. Dai and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 63, no. 5, pp. 1996-2002, May 2016. (SCI, EI)

“Area-efficient and low-leakage diode string for on-chip ESD protection,”

C.-Y. Lin, P.-H. Wu, and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 63, no. 2, pp. 531-536, Feb. 2016. (SCI, EI)

“Area-efficient ESD clamp circuit with a capacitance-boosting technique to minimize standby leakage current,”

F. A. Altolaguirre and Ming-Dou Ker

IEEE Trans. on Device and Materials Reliability, vol. 15, no. 2, pp. 156-162, Jun. 2015. (SCI, EI)

“Latch-up protection design with corresponding complementary current to suppress the effect of external current triggers,”

H.-W. Tsai and Ming-Dou Ker

IEEE Trans. on Device and Materials Reliability, vol. 15, no. 2, pp. 242-249, Jun. 2015. (SCI, EI)

“Active guard ring to improve latch-up immunity,”

H.-W. Tsai and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 61, no. 12, pp. 4145-4152, Dec. 2014. (SCI, EI)

“On-chip transient voltage suppressor integrated with silicon-based transceiver IC for system-level ESD protection,”

C.-H. Chuang and Ming-Dou Ker

IEEE Trans. on Industrial Electronics, vol. 61, no. 10, pp. 5615-5621, Oct. 2014. (SCI, EI)

“Investigating electron depletion effect in amorphous indium-gallium-zinc-oxide thin-film transistor with a floating capping metal by technology computer-aided design simulation and leakage reduction,”

T.-C. Lu, W.-T. Chen, H.-W. Zan, and Ming-Dou Ker

Jpn. J. Appl. Phys. , vol. 53, no. 6, pp. 064302, Jun. 2014.

“Local CDM ESD protection circuits for cross-power domains in 3D IC applications,”

S.-H. Chen, D. Linten, M. Scholz, Y.-C. Huang, G. Hellings, R. Boschke, Ming-Dou Ker and G. Groeseneken

IEEE Trans. on Device and Materials Reliability, vol. 14, no. 2, pp. 781-783, Jun. 2014. (SCI, EI)

“Through diffusion tensor magnetic resonance imaging to evaluate the original properties of neural pathways of patients with partial seizures and secondary generalization by individual anatomic reference atlas,”

S.-J. Peng, T. Harnod, J.-Z. Tsai, C.-C. Huang, Ming-Dou Ker, J.-C. Chiou, H. Chiueh, C.-Y. Wu, and Y.-L. Hsin

BioMed Research International, vol. 2014, May 2014. (SCI, EI)

“Design of high-voltage-tolerant stimulus driver with adaptive loading consideration to suppress epileptic seizure in a 0.18-μm CMOS process,”

C.-Y. Lin, Y.-J. Li, and Ming-Dou Ker

International Journal of Analog Integrated Circuits and Signal Processing, Springer US, vol. 79, no. 2, pp. 219-226, May 2014. (SCI, EI)

“On the design of power-rail ESD clamp circuits with gate leakage consideration in nanoscale CMOS technology,”

Ming-Dou Ker and C.-T. Yeh

IEEE Trans. on Device and Materials Reliability, vol. 14, no. 1, pp. 536-544, Mar. 2014. (SCI, EI)

“Layout consideration and circuit solution to prevent EOS failure induced by latchup test in a high-voltage integrated circuits,”

H.-W. Tsai and Ming-Dou Ker

IEEE Trans. on Device and Materials Reliability, vol. 14, no. 1, pp. 493-498, Mar. 2014. (SCI, EI)

“A fully integrated 8-channel closed-loop neural-prosthetic CMOS SoC for real-time epileptic seizure control,”

W.-M. Chen, H. Chiueh, T.-J. Chen, C.-L. Ho, C. Jeng, Ming-Dou Ker, C.-Y. Lin, Y.-C. Huang, C.-W. Chou, T.-Y. Fan, M.-S. Cheng, Y.-L. Hsin, S.-F. Liang, Y.-L. Wang, F.-Z. Shaw, Y.-H. Huang, C.-H. Yang, and C.-Y. Wu

IEEE Journal of Solid-State Circuits, vol. 49, no. 1, pp. 232-247, Jan. 2014. (SCI, EI)

“SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance,”

Ming-Dou Ker, W.-Y. Lin, and C.-C. Yen

Microelectronics Reliability, vol. 54, no. 1, pp. 71-78, Jan. 2014. (SCI, EI)

“Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit,”

P.-Y. Chiu and Ming-Dou Ker

Microelectronics Reliability, vol. 54, no. 1, pp. 64-70, Jan. 2014. (SCI, EI)

“Robust ESD Protection Design for 40-Gbs Transceiver in 65-nm CMOS Process,”

C.-Y. Lin, L.-W. Chu, and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 60, no. 11, pp. 3625-3631, Nov. 2013. (SCI, EI)

“Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process,”

F. A. Altolaguirre and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 60, no. 10, pp. 3500-3507, Oct. 2013. (SCI, EI)

“Design of 2×VDD-tolerant I/O buffer with PVT compensation realized by only 1×VDD thin-oxide devices,”

Ming-Dou Ker and P.-Y. Chiu

IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 60, no. 10, pp. 2549-2560, Oct. 2013. (SCI, EI)

“A latchup-immune and robust SCR device for ESD protection in 0.25-μm 5-V CMOS process,”

Y.-C. Huang and Ming-Dou Ker

IEEE Electron Device Letters, vol. 34, no. 5, pp. 674-676, May 2013. (SCI, EI)

“Implantable stimulator for epileptic seizure suppression with loading impedance adaptability,”

C.-Y. Lin, W.-L. Chen, and Ming-Dou Ker

IEEE Trans. on Biomedical Circuits and Systems, vol. 7, no. 2, pp. 196-203, Apr. 2013. (SCI, EI)

“High area-efficient ESD clamp circuit with equivalent RC-based detection mechanism in a 65-nm CMOS process,”

C.-T. Yeh and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 60, no. 3, pp. 1011-1018, Mar. 2013. (SCI, EI)

“Design of dual-band ESD protection for 24-/60-GHz millimeter-wave circuits,”

C.-Y. Lin, L.-W. Chu, and Ming-Dou Ker

IEEE Trans. on Device and Materials Reliability, vol. 13, no. 1, pp. 110-118, Mar. 2013. (SCI, EI)

“Large-swing-tolerant ESD protection circuit for gigahertz power amplifier in a 65-nm CMOS process,”

C.-Y. Lin, S.-Y. Tsai, L.-W. Chu, and Ming-Dou Ker

IEEE Trans. on Microwave Theory and Techniques, vol. 61, no. 2, pp. 914-921, Feb. 2013. (SCI, EI)

“PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit,”

C.-T. Yeh and Ming-Dou Ker

Microelectronics Reliability, vol. 53, no. 2, pp. 208-214, Feb. 2013. (SCI, EI)

“Overview of on-chip stimulator designs for biomedical applications,”

C.-Y. Lin and Ming-Dou Ker

Journal of Neuroscience and Neuroengineering, vol. 1, no. 2, pp. 204-212, Dec. 2012.

“Resistor-less design of power-rail ESD clamp circuit in nanoscale CMOS technology,”

C.-T. Yeh and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 59, no. 12, pp. 3456-3463, Dec. 2012. (SCI, EI)

“Investigation on CDM ESD events at core circuits in a 65-nm CMOS process,”

C.-Y. Lin, T.-L. Chang, and Ming-Dou Ker

Microelectronics Reliability, vol. 52, no. 11, pp. 2627-2631, Nov. 2012. (SCI, EI)

“Power-rail ESD clamp circuit with ultralow standby leakage current and high area efficiency in nanometer CMOS technology,”

C.-T. Yeh and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 59, no. 10, pp. 2626-2634, Oct. 2012. (SCI, EI)

“Design of compact ESD protection circuit for V-band RF applications in a 65-nm CMOS technology,”

C.-Y. Lin, L.-W. Chu, S.-Y. Tsai, and Ming-Dou Ker

IEEE Trans. on Device and Materials Reliability, vol. 12, no. 3, pp. 554-561, Sep. 2012. (SCI, EI)

“Characterization of SOA in time domain and the improvement techniques for using in high-voltage integrated circuits,”

W.-Y. Chen and Ming-Dou Ker

IEEE Trans. on Device and Materials Reliability, vol. 12, no. 2, pp. 382-390, Jun. 2012. (SCI, EI)

“Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications,”

C.-T. Yeh and Ming-Dou Ker

Microelectronics Reliability, vol. 52, no. 6, pp. 1020-1030, Jun. 2012. (SCI, EI)

“ESD protection design for 60-GHz LNA with inductor-triggered SCR in 65-nm CMOS process,”

C.-Y. Lin, L.-W. Chu, and Ming-Dou Ker

IEEE Trans. on Microwave Theory and Techniques, vol. 60, no. 3, pp. 714-723, Mar. 2012. (SCI, EI)

“Diode-triggered silicon-controlled rectifier with reduced voltage overshoot for CDM ESD protection,”

W.-Y. Chen, E. Rosenbaum, and Ming-Dou Ker

IEEE Trans. on Device and Materials Reliability, vol. 12, no. 1, pp. 10-14, Mar. 2012. (SCI, EI)

“New design of 2 x tmes VDD-tolerant power-rail ESD clamp circuit for mixed-voltage IO buffers in 65-nm CMOS technology,”

C.-T. Yeh and Ming-Dou Ker

IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 59, no. 3, pp. 178-182, Mar. 2012. (SCI, EI)

“New 4-bit transient-to-digital converter for system-level ESD protection in display panels,”

Ming-Dou Ker and C.-C. Yen

IEEE Trans. on Industrial Electronics, vol. 59, no. 2, pp. 1278-1287, Feb. 2012. (SCI, EI)

“Design of integrated gate driver with threshold voltage drop cancellation in amorphous silicon technology for TFT-LCD application,”

L.-W. Chu, P.-T. Liu, and Ming-Dou Ker

IEEE Journal of Display Technology, vol. 7, no. 12, pp. 657-664, Dec. 2011. (SCI, EI)

“Stimulus driver for epilepsy seizure suppression with adaptive loading impedance,”

Ming-Dou Ker, C.-Y. Lin, and W.-L. Chen

Journal of Neural Engineering, vol. 8, no. 6, Dec. 2011. (SCI, EI)

“New low-leakage power-rail ESD clamp circuit in a 65-nm low-voltage CMOS process,”

Ming-Dou Ker and P.-Y. Chiu

IEEE Trans. on Device and Materials Reliability, vol. 11, no. 3, pp. 474-483, Sep. 2011. (SCI, EI)

“Improving safe operating area of nLDMOS array with embedded silicon controlled rectifier for ESD protection in a 24-V BCD process,”

W.-Y. Chen and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 58, no. 9, pp. 2944-2951, Sep. 2011. (SCI, EI)

“Digital time-modulation pixel memory circuit in LTPS technology,”

S.-H. Chen, Ming-Dou Ker, and T.-M. Wang

Journal of Society for Information Display, vol. 19, no. 8, pp. 539-546, Aug. 2011. (SCI, EI)

“Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process,”

C.-Y. Lin, L.-W. Chu, and Ming-Dou Ker

Microelectronics Reliability, vol. 51, no. 8, pp. 1315-1324, Aug. 2011. (SCI, EI)

“Design and implementation of readout circuit on glass substrate with digital correction for touch-panel applications,”

T.-M. Wang and Ming-Dou Ker

Journal of Society for Information Display, vol. 19, no. 7, pp. 463-470, Jul. 2011. (SCI, EI)

“Overview on ESD protection designs of low parasitic capacitance for RF ICs in CMOS technologies,”

Ming-Dou Ker, C.-Y. Lin, and Y.-W. Hsiao

IEEE Trans. on Device and Materials Reliability, vol. 11, no. 2, pp. 207-218, Jun. 2011. (SCI, EI)

“Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS process,”

Y.-H. Weng, H.-W. Tsai, and Ming-Dou Ker

Microelectronics Reliability, vol. 51, no. 5, pp. 871-878, May 2011. (SCI, EI)

“Design and implementation of readout circuit with threshold voltage compensation on glass substrate for touch panel applications,”

Y.-T. Lin, Ming-Dou Ker, and T.-M. Wang

Japanese Journal of Applied Physics, vol. 50, no. 3, pp. (03CC07-1)-(03CC07-6), Mar. 2011. (SCI, EI)

“Electrostatic discharge protection design for high-voltage programming pin in fully-silicided CMOS ICs,”

Ming-Dou Ker, W.-Y. Chen, W.-T. Shieh, and I-J. Wei

IEEE Journal of Solid-State Circuits, vol. 46, no. 2, pp. 537-545, Feb. 2011. (SCI, EI)

“Design of analog pixel memory for low power application in TFT-LCDs,”

L.-W. Chu, P.-T. Liu, and Ming-Dou Ker

IEEE Journal of Display Technology, vol. 7, no. 2, pp. 62-69, Feb. 2011. (SCI, EI)

“ESD protection design with lateral DMOS transistor in 40-V BCD technology,”

C.-T. Wang and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 57, no. 12, pp. 3395-3404, Dec. 2010. (SCI, EI)

“Capacitor-less design of power-rail ESD clamp circuit with adjustable holding voltage for on-chip ESD protection,”

C.-T. Yeh and Ming-Dou Ker

IEEE Journal of Solid-State Circuits, vol. 45, no. 11, pp. 2476-2486, Nov. 2010. (SCI, EI)

“Implementation of delta-sigma analog-to-digital converter in LTPS process,”

C.-C. Tsai, T.-M. Wang, and Ming-Dou Ker

Journal of Society for Information Display, vol. 18, no. 11, pp. 904-912, Nov. 2010. (SCI, EI)

“New transient detection circuit for on-chip protection design against system-level electrical transient disturbance,”

Ming-Dou Ker and C.-C. Yen

IEEE Trans. on Industrial Electronics, vol. 57, no. 10, pp. 3533-3543, Oct. 2010. (SCI, EI)

“Design and implementation of readout circuit on glass substrate for touch panel applications,”

T.-M. Wang and Ming-Dou Ker

IEEE Journal of Display Technology, vol. 6, no. 8, pp. 290-297, Aug. 2010. (SCI, EI)

“High-voltage-tolerant ESD clamp circuit with low standby leakage in nanoscale CMOS process,”

Ming-Dou Ker and C.-Y. Lin

IEEE Trans. on Electron Devices, vol. 57, no. 7, pp. 1636-1641, Jul. 2010. (SCI, EI)

“Design of 2xVDD-tolerant power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm CMOS technology,”

C.-T. Wang and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 57, no. 6, pp. 1460-1465, Jun. 2010. (SCI, EI)

“Optimization on layout style of ESD protection diode for radio-frequency front-end and high-speed I/O interface circuits,”

C.-T. Yeh, Ming-Dou Ker, and Y.-C. Liang

IEEE Trans. on Device and Materials Reliability, vol. 10, no. 2, pp. 238-246, Jun. 2010. (SCI, EI)

“Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme,”

C.-Y. Lin, Ming-Dou Ker, and Y.-W. Hsiao

Microelectronics Reliability, vol. 50, no. 6, pp. 831-838, Jun. 2010. (SCI, EI)

“Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technology,”

S.-H. Chen and Ming-Dou Ker

Microelectronics Reliability, vol. 50, no. 6, pp.821-830, Jun. 2010. (SCI, EI)

“Circuit and layout co-design for ESD protection in bipolar-CMOS- DMOS (BCD) high-voltage process,”

W.-Y. Chen and Ming-Dou Ker

IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 57, no. 5, pp. 1039-1047, May 2010. (SCI, EI)

“New layout arrangement to improve ESD robustness of large-array high-voltage nLDMOS,”

W.-Y. Chen and Ming-Dou Ker

IEEE Electron Device Letters, vol. 31, no. 2, pp. 159-161, Feb. 2010. (SCI, EI)

“Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation,”

H.-W. Tsai and Ming-Dou Ker

Microelectronics Reliability, vol. 50, no. 1, pp. 48-56, Jan. 2010. (SCI, EI)

“New ballasting layout schemes to improve ESD robustness of I/O buffers in fully silicided CMOS process,”

Ming-Dou Ker, W.-Y. Chen, W.-T. Shieh, and I-J. Wei

IEEE Trans. on Electron Devices, vol. 56, no. 12, pp.3149-3159, Dec. 2009. (SCI, EI)

“Digital-to-Analog converter with gamma correction on glass substrate for TFT panel application,”

T.-M. Wang, Y.-H. Li, and Ming-Dou Ker

Journal of Society for Information Display, vol. 17, no. 10, pp. 785-794, Oct. 2009. (SCI, EI)

“Design of analog output buffer with level shifting function on glass substrate for panel application,”

T.-M. Wang, Ming-Dou Ker, and S.-C. Chen

IEEE/OSA Journal of Display Technology, vol. 5, no. 9, pp.368-375, Sep. 2009. (EI)

“Transient-to-digital converter for system-level electrostatic discharge protection in CMOS ICs,”

Ming-Dou Ker and C.-C. Yen

IEEE Trans. on Electromagnetic Compatibility, vol.51, no. 3, pp. 620-630, Aug. 2009. (SCI, EI)

“Impact of gate leakage on performances of phase-locked loop circuit in nanoscale CMOS technology,”

J.-S. Chen and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 56, no. 8, pp. 1774-1779, Aug. 2009. (SCI, EI)

“Optimization on MOS-triggered SCR structures for on-chip ESD protection,”

S.-H. Chen and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol.56, no. 7, pp. 1466-1472, Jul. 2009. (SCI, EI)

“Transient-induced latchup in CMOS ICs under electrical fast-transient test,”

C.-C. Yen, Ming-Dou Ker, and T.-Y. Chen

IEEE Trans. on Device and Materials Reliability, vol. 9, no. 2, pp. 255-264, Jun. 2009. (SCI, EI)

“The effect of IEC-like fast transients on RC-triggered ESD power clamps,”

C.-C. Yen and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 56, no. 6, pp. 1204-1210, Jun. 2009. (SCI, EI)

“Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process,”

Y.-W. Hsiao and Ming-Dou Ker

Microelectronics Reliability, vol. 49, no. 6, pp. 650-659, Jun. 2009. (SCI, EI)

“A 5-GHz differential low-noise amplifier with high pin-to-pin ESD robustness in a 130-nm CMOS process,”

Y.-W. Hsiao and Ming-Dou Ker

IEEE Trans. on Microwave Theory and Techniques, vol. 57, no. 5, pp. 1044-1053, May 2009. (SCI, EI)

“Design of mixed-voltage-tolerant crystal oscillator circuit in low-voltage CMOS technology,”

T.-M. Wang, Ming-Dou Ker, and H.-T. Liao

IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 56, no. 5, pp. 966-974, May 2009. (SCI, EI)

“Area-efficient ESD-transient detection circuit with smaller capacitance for on-chip power-rail ESD protection in CMOS ICs,”

S.-H. Chen and Ming-Dou Ker

IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 56, no. 5, pp. 359-363, May 2009. (SCI, EI)

“High-voltage nLDMOS in waffle-layout style with body-injected technique for ESD protection,”

W.-Y. Chen and Ming-Dou Ker

IEEE Electron Device Letters, vol. 30, no. 4, pp. 389-391, Apr. 2009. (SCI, EI)

“Design of power-rail ESD clamp circuit with ultra-low standby leakage current in nanoscale CMOS technology,”

C.-T. Wang and Ming-Dou Ker

IEEE Journal of Solid-State Circuits, vol. 44, no. 3, pp. 956-964, Mar. 2009. (SCI, EI)

“Design of high-voltage-tolerant ESD protection circuit in low-voltage CMOS processes,”

Ming-Dou Ker and C.-T. Wang

IEEE Trans. on Device and Materials Reliability, vol. 9, no. 1, pp. 49-58, Mar. 2009. (SCI, EI)

“Board level ESD of driver ICs on LCD panel,”

J.-C. Tseng, C.-T. Hsu, C.-K. Tsai, S.-C. Chen, and Ming-Dou Ker

IEEE Trans. on Device and Materials Reliability, vol. 9, no. 1, pp. 59-64, Mar. 2009. (SCI, EI)

“Impedance-isolation technique for ESD protection design in RF integrated circuits,”

Ming-Dou Ker and Y.-W. Hsiao

IEICE Trans. on Electronics, vol. E92-C, no. 3, pp. 341-351, Mar. 2009. (SCI, EI)

“Investigation on board-level CDM ESD issue in IC products,”

Ming-Dou Ker and Y.-W. Hsiao

IEEE Trans. on Device and Materials Reliability, vol. 8, no. 4, pp. 694-704, Dec. 2008. (SCI, EI)

“Investigation and design of on-chip power-rail ESD clamp circuits without suffering latchup-like failure during system-level ESD test,”

Ming-Dou Ker and C.-C. Yen

IEEE Journal of Solid-State Circuits, vol. 43, no. 11, pp. 2533-2545, Nov. 2008. (SCI, EI)

“Investigation on robustness of CMOS devices against cable discharge event (CDE) under different layout parameters in deep-submicron CMOS technology,”

Ming-Dou Ker and T.-H. Lai

IEEE Trans. on Electromagnetic Compatibility, vol. 50, no. 4, pp. 810-821, Nov. 2008. (SCI, EI)

“Temperature coefficient of poly-silicon TFT and its application on voltage reference circuit with temperature compensation in LTPS process,”

T.-C. Lu, H.-W. Zan, and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 55, no. 10, pp. 2583-2589, Oct. 2008. (SCI, EI)

“Active ESD protection design for interface circuits between separated power domains against cross-power-domain ESD stresses,”

S.-H. Chen, Ming-Dou Ker, and H.-P. Hung

IEEE Trans. on Device and Materials Reliability, vol. 8, no. 3, pp. 549-560, Sep. 2008. (SCI, EI)

“Low-capacitance and fast turn-on SCR for RF ESD protection,”

C.-Y. Lin, Ming-Dou Ker, and G.-X. Meng

IEICE Trans. on Electronics, vol. E91-C, no. 8, pp. 1321-1330, Aug. 2008. (SCI, EI)

“Investigation on the validity of holding voltage in high-voltage devices measured by transmission-line-pulsing (TLP),”

W.-Y. Chen, Ming-Dou Ker, and Y.-J. Huang

IEEE Electron Device Letters, vol. 29, no. 7, pp. 762-764, Jul. 2008. (SCI, EI)

“ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers,”

Ming-Dou Ker and W.-J. Chang

IEEE Trans. on Electron Devices, vol. 55, no. 6, pp. 1409-1416, Jun. 2008. (SCI, EI)

“Impact of MOSFET gate-oxide reliability on CMOS operational amplifier in a 130-nm low-voltage process,”

Ming-Dou Ker and J.-S. Chen

IEEE Trans. on Device and Materials Reliability, vol. 8, no. 2, pp. 394-405, Jun. 2008. (SCI, EI)

“Low-capacitance SCR with waffle layout structure for on-chip ESD protection in RF ICs,”

Ming-Dou Ker and C.-Y. Lin

IEEE Trans. on Microwave Theory and Techniques, vol. 56, no. 5, pp. 1286-1294, May 2008. (SCI, EI)

“Circuit performance degradation of switched-capacitor circuit with bootstrapped technique due to gate-oxide overstress in a 130-nm CMOS process,”

J.-S. Chen and Ming-Dou Ker

IEICE Trans. on Electronics, vol. E91-C, no. 3, pp. 378-384, Mar. 2008. (SCI, EI)

“On-chip transient detection circuit for system-level ESD protection in CMOS integrated circuits to meet electromagnetic compatibility regulation,”

Ming-Dou Ker, C.-C. Yen, and P.-C. Shih

IEEE Trans. on Electromagnetic Compatibility, vol. 50, no. 1, pp. 13-21, Feb. 2008. (SCI, EI)

“The impact of gate-oxide breakdown on common-source amplifiers with diode-connected active load in low-voltage CMOS processes,”

J.-S. Chen and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 54, no. 11, pp. 2860-2870, Nov. 2007. (SCI, EI)

“On-chip ESD protection design for automotive vacuum-fluorescent-display (VFD) driver IC to sustain high ESD stress,”

Ming-Dou Ker and W.-J. Chang

IEEE Trans. on Device and Materials Reliability, vol. 7, no. 3, pp. 438-445, Sep. 2007. (SCI, EI)

“New gate-bias voltage-generating technique with threshold-voltage compensation for on-glass analog circuits in LTPS process,”

J.-S. Chen and Ming-Dou Ker

IEEE/OSA Journal of Display Technology, vol. 3, no. 3, pp. 309-314, Sep. 2007. (EI)

“Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits,”

S.-H. Chen and Ming-Dou Ker

Microelectronics Reliability, vol. 47, no. 9-11, pp. 1502-1505, Sep. 2007. (SCI, EI)

“Transient-induced latchup dependence on power-pin damping frequency and damping factor in CMOS integrated circuits,”

S.-F. Hsu and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 54, no. 8, pp. 2002-2010, Aug. 2007. (SCI, EI)

“The impact of drift implant and layout parameters on ESD robustness for on-chip ESD protection devices in 40-V CMOS technology,”

W.-J. Chang and Ming-Dou Ker

IEEE Trans. on Device and Materials Reliability, vol. 7, no. 2, pp. 324-332, Jun. 2007. (SCI, EI)

“Fabrication of a miniature CMOS-based optical biosensor,”

W.-J. Ho, J.-S. Chen, Ming-Dou Ker, T.-K. Wu, C.-Y. Wu, Y.-S. Yang, Y.-K. Li, and C.-J. Yuan

Biosensors and Bioelectronics, vol. 22, no. 12, pp. 3008-3013, Jun. 2007. (SCI, EI)

“ESD protection design with low-capacitance consideration for high-speed/high-frequency I/O interfaces in integrated circuits,”

Ming-Dou Ker and Y.-W. Hsiao

Recent Patents on Engineering, vol. 1, no. 2, pp. 131-145, Jun. 2007.

“Implementation of initial-on ESD protection concept with PMOS-triggered SCR devices in deep-submicron CMOS technology,”

Ming-Dou Ker and S.-H. Chen

IEEE Journal of Solid-State Circuits, vol. 42, no. 5, pp. 1158-1168, May 2007. (SCI, EI)

“Dependence of device structures on latchup immunity in a high-voltage 40-V CMOS process with drain-extended MOSFETs,”

S.-F. Hsu and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 54, no. 4, pp. 840-851, Apr. 2007. (SCI, EI)

“Bond pad design with low capacitance in CMOS technology for RF applications,”

Y.-W. Hsiao and Ming-Dou Ker

IEEE Electron Device Letters, vol. 28, no. 1, pp. 68-70, Jan. 2007. (SCI, EI)

“An output buffer for 3.3-V applications in a 0.13-µm 1/2.5-V CMOS process,”

S.-L. Chen and Ming-Dou Ker

IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 54, no. 1, pp. 14-18, Jan. 2007. (SCI, EI)

“Ultra-high-voltage charge pump circuit in low-voltage bulk CMOS processes with polysilicon diodes,”

Ming-Dou Ker and S.-L. Chen

IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 54, no. 1, pp. 47-51, Jan. 2007. (SCI, EI)

“Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology,”

Ming-Dou Ker and W.-J. Chang

Microelectronics Reliability, vol. 47, no. 1, pp. 27-35, Jan. 2007. (SCI, EI)

“ESD-protection design with extra low-leakage-current diode string for RF circuits in SiGe BiCMOS process,”

Ming-Dou Ker, Y.-W. Hsiao, and W.-L. Wu

IEEE Trans. on Device and Materials Reliability, vol. 6, no. 4, pp. 517-527, Dec. 2006. (SCI, EI)

“ESD robustness of thin-film devices with different layout structures in LTPS technology,”

C.-K. Deng and Ming-Dou Ker

Microelectronics Reliability, vol. 46, no. 12, pp. 2067-2073, Dec. 2006. (SCI, EI)

“Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices,”

Ming-Dou Ker and J.-H. Chen

IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2601-2609, Nov. 2006. (SCI, EI)

“Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process,”

Ming-Dou Ker, W.-Y. Chen, and K.-C. Hsu

IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 53, no. 10, pp. 2187-2193, Oct. 2006. (SCI, EI)

“Design of mixed-voltage I/O buffer by using NMOS-blocking technique,”

Ming-Dou Ker and S.-L. Chen

IEEE Journal of Solid-State Circuits, vol. 41, no. 10, pp. 2324-2333, Oct. 2006. (SCI, EI)

“Component-level measurement for transient-induced latchup in CMOS ICs under system-level ESD considerations,”

Ming-Dou Ker and S.-F. Hsu

IEEE Trans. on Device and Materials Reliability, vol. 6, no. 3, pp. 461-472, Sep. 2006. (SCI, EI)

“Overview and design of mixed-voltage I/O buffers with low-voltage thin-oxide CMOS transistors,”

Ming-Dou Ker, S.-L. Chen, and C.-S. Tsai

IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 53, no. 9, pp. 1934-1945, Sep. 2006. (SCI, EI)

“New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation,”

Ming-Dou Ker and J.-S. Chen

IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 53, no. 8, pp. 667-671, Aug. 2006. (SCI, EI)

“Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology,”

S.-H. Chen and Ming-Dou Ker

Microelectronics Reliability, vol. 46, no. 7, pp. 1042-1049, Jul. 2006. (SCI, EI)

“On-panel output buffer with offset compensation technique for data driver in LTPS technology,”

Ming-Dou Ker, C.-K. Deng, and J.-L. Huang

IEEE/OSA Journal of Display Technology, vol. 2, no. 2, pp. 153-159, Jun. 2006. (EI)

“Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes,”

Ming-Dou Ker, S.-L. Chen, and C.-S. Tsai

IEEE Journal of Solid-State Circuits, vol. 41, no. 5, pp. 1100-1107, May 2006. (SCI, EI)

“ESD failure mechanisms of analog I/O cells in a 0.18-µm CMOS technology,”

Ming-Dou Ker, S.-H. Chen, and C.-H. Chuang

IEEE Trans. on Device and Materials Reliability, vol. 6, no. 1, pp. 102-111, Mar. 2006. (SCI, EI)

“Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board,”

K.-H. Lin and Ming-Dou Ker

Microelectronics Reliability, vol. 46, no. 2-4, pp. 301-310, Feb.-Apr. 2006. (SCI, EI)

“Evaulation on board-level noise filter networks to suppress transient-induced latchup in CMOS ICs under system-level ESD test,”

Ming-Dou Ker and S.-F. Hsu

IEEE Trans. on Electromagnetic Compatibility, vol. 48, no. 1, pp. 161-171, Feb. 2006. (SCI, EI)

“Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations,”

Ming-Dou Ker and K.-H. Lin

IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 53, no. 2, pp. 235-246, Feb. 2006. (SCI, EI)

“Optimization of broadband RF performance and ESD robustness by π-model distributed ESD protection scheme,”

Ming-Dou Ker, B.-J. Kuo, and Y.-W. Hsiao

Journal of Electrostatics, vol. 64, no. 2, pp. 80-87, Feb. 2006. (SCI, EI)

“ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology,”

Ming-Dou Ker and K.-H. Lin

IEEE Journal of Solid-State Circuits, vol. 40, no. 11, pp. 2329-2338, Nov. 2005. (SCI, EI)

“A CMOS bandgap reference circuit for sub-1-V operation without using extra low-threshold-voltage device,”

Ming-Dou Ker and J.-S. Chen

IEICE Trans. on Electronics, vol. E88-C, no. 11, pp. 2150-2155, Nov. 2005. (SCI, EI)

“Investigation on seal-ring rules for IC product reliability in 0.25-µm CMOS technology,”

S.-H. Chen and Ming-Dou Ker

Microelectronics Reliability, vol. 45, no. 9-11, pp. 1311-1316, Sep.-Nov. 2005. (SCI, EI)

“ESD protection design of low-voltage-triggered p-n-p devices and their failure modes in mixed-voltage I/O interfaces with signal levels higher than VDD and lower than VSS,”

Ming-Dou Ker and W.-J. Chang

IEEE Trans. on Device and Materials Reliability, vol. 5, no. 3, pp. 602-612, Sep. 2005. (SCI, EI)

“ESD protection design for 1- to 10-GHz distributed amplifier in CMOS technology,”

Ming-Dou Ker, Y.-W. Hsiao, and B.-J. Kuo

IEEE Trans. on Microwave Theory and Techniques, vol. 53, no. 9, pp. 2672-2681, Sep. 2005. (SCI, EI)

“Native-NMOS-Triggered SCR With Faster Turn-On Speed for Effectively ESD Protection in a 0.13-µm CMOS Process,”

Ming-Dou Ker and K.-C. Hsu

IEEE Trans. on Device and Materials Reliability, vol. 5, no. 3, pp. 543-554, Sep. 2005. (SCI, EI)

“Physical mechanism and device simulation on transient-induced latchup in CMOS ICs under system-level ESD test,”

Ming-Dou Ker and S.-F. Hsu

IEEE Trans. on Electron Devices, vol. 52, no. 8, pp. 1821-1831, Aug. 2005. (SCI, EI)

“The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs,”

Ming-Dou Ker and K.-H. Lin

IEEE Journal of Solid-State Circuits, vol. 40, no. 8, pp. 1751-1759, Aug. 2005. (SCI, EI)

“A new Schmitt trigger circuit in a 0.13-μm 1/2.5-V CMOS process to receive 3.3-V input signals,”

S.-L. Chen and Ming-Dou Ker

IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 52, no. 7, pp. 361-365, Jul. 2005. (SCI, EI)

“Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits,”

Ming-Dou Ker and K.-C. Hsu

IEEE Trans. on Device and Materials Reliability, vol. 5, no. 2, pp. 235-249, Jun. 2005. (SCI, EI)

“SCR device fabricated with dummy-gate structure to improve turn-on speed for effective ESD protection in CMOS technology,”

Ming-Dou Ker and K.-C. Hsu

IEEE Trans. on Semiconductor Manufacturing, vol. 18, no. 2, pp. 320-327, May 2005. (SCI, EI)

“ESD implantations for on-chip ESD protection with layout consideration in 0.18-μm salidided CMOS technology,”

Ming-Dou Ker, C.-H. Chuang, and W.-Y. Lo

IEEE Trans. on Semiconductor Manufacturing, vol. 18, no. 2, pp. 328-337, May 2005. (SCI, EI)

“MOS-bounded diodes for on-chip ESD protection in deep submicron CMOS process,”

Ming-Dou Ker, K.-H. Lin, and C.-H. Chuang

IEICE Trans. on Electronics, vol. E88-C, no. 3, pp. 429-436, Mar. 2005. (SCI, EI)

“Decreasing-size distributed ESD protection scheme for broadband RF circuits,”

Ming-Dou Ker and B.-J. Kuo

IEEE Trans. on Microwave Theory and Techniques, vol. 53, no. 2, pp. 582-589, Feb. 2005. (SCI, EI)

“ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit,”

Ming-Dou Ker and H.-C. Hsu

IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 52, no. 1, pp. 44-53, Jan. 2005. (SCI, EI)

“SCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-µm fully salicided CMOS process,”

Ming-Dou Ker and Z.-P. Chen

IEEE Trans. on Electron Devices, vol. 51, no. 10, pp. 1731-1733, Oct. 2004. (SCI, EI)

“On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in sub-quarter-micron CMOS process,”

Ming-Dou Ker, K.-H. Lin, and C.-H. Chuang

IEEE Trans. on Electron Devices, vol. 51, no. 10, pp. 1628-1635, Oct. 2004. (SCI, EI)

“Double snapback characteristics in high-voltage nMOFETs and the impact to on-chip ESD protection design,”

Ming-Dou Ker and K.-H. Lin

IEEE Electron Device Letters, vol. 25, no. 9, pp. 640-642, Sep. 2004. (SCI, EI)

“ESD protection design to overcome internal damage on interface circuits of a CMOS IC with multiple separated power pins,”

Ming-Dou Ker, C.-Y. Chang, and Y.-S. Chang

IEEE Trans. on Components and Packaging Technologies, vol. 27, no. 3, pp. 445-451, Sep. 2004. (SCI, EI)

“Investigation on device characteristics of MOSFET transistor placed under bond pad for high-pin-count SOC applications,”

Ming-Dou Ker and J.-J. Peng

IEEE Trans. on Components and Packaging Technologies, vol. 27, no. 3, pp. 452-460, Sep. 2004. (SCI, EI)

“Design on ESD protection schemes for IC with power-down-mode operation,”

Ming-Dou Ker and K.-H. Lin

IEEE Journal of Solid-State Circuits, vol. 39, no. 8, pp. 1378-1382, Aug. 2004. (SCI, EI)

“Double-triggered SCR with enhanced turn-on speed for effective ESD protection in nano-scale CMOS technology,”

Ming-Dou Ker, K.-C. Hsu, and H.-C. Hsu

WSEAS Trans. on Electronics, vol. 1, no. 2, pp. 256-263, Apr. 2004.

“Abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing non-connected balls,”

W.-Y. Lo and Ming-Dou Ker

IEEE Trans. on Device and Materials Reliability, vol. 4, no.1, pp. 24-31, Mar. 2004. (SCI, EI)

Microelectronics Reliability, vol. 44, no. 2, pp. 213-221, Feb. 2004. (SCI, EI)

“Active electrostatic discharge (ESD) device for on-chip ESD protection in sub-quarter-micron complementary metal-oxide semiconductor (CMOS) process,”

Ming-Dou Ker and T.-K. Tseng

Japanese Journal of Applied Physics (JJAP) Part 2, Letters, vol. 43, no. 1A/B, pp. L33-L35, Jan. 2004. (SCI, EI)

“ESD protection scheme for I/O interface of CMOS IC operating in the power-down mode on system board,”

K.-H. Lin and Ming-Dou Ker

WSEAS Trans. on Electronics, vol. 1, no. 1, pp. 219-225, Jan. 2004.

“Dummy-gate structure to improve turn-on speed of silicon-controlled rectifier (SCR) device for effective electrostatic discharge (ESD) protection,”

Ming-Dou Ker and K.-C. Hsu

Japanese Journal of Applied Physics (JJAP) Part 2, Letters, vol. 42, no. 11B, pp. L1366-L1368, Nov. 2003. (SCI, EI)

“Analysis and prevention on NC-ball induced ESD damages in a 683-pin BGA packaged chipset IC,”

W.-Y. Lo and Ming-Dou Ker

Microelectronics Reliability, vol. 43, no. 9-11, pp. 1583-1588, Sep.-Nov. 2003. (SCI, EI)

“ESD Implantation for sub-quarter-micron CMOS technology to enhance ESD robustness,”

Ming-Dou Ker, H.-C. Hsu, and J.-J. Peng

IEEE Trans. on Electron Devices, vol. 50, no. 10, pp. 2126-2134, Oct. 2003. (SCI, EI)

“SCR devices with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes,”

Ming-Dou Ker and K.-C. Hsu

IEEE Trans. on Device and Materials Reliability, vol. 3, no 3, pp. 58-68, Sep. 2003. (SCI, EI)

“Latchup-free ESD protection design with complementary substrate-triggered SCR devices,”

Ming-Dou Ker and K.-C. Hsu

IEEE Journal of Solid-State Circuits, vol. 38, no. 8, pp. 1380-1392, Aug. 2003. (SCI, EI)

“Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process,”

T.-Y. Chen and Ming-Dou Ker

IEEE Trans. on Semiconductor Manufacturing, vol. 16, no. 3, pp. 486-500, Aug. 2003. (SCI, EI)

“Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product,”

I.-C. Lin, C.-Y. Huang, C.-J. Chao, and Ming-Dou Ker

Microelectronics Reliability, vol. 43, no. 8, pp. 1295-1301, Aug. 2003. (SCI, EI)

“High-current characterization of polysilicon diode for electrostatic discharge protection in sub-quarter-micron complementary metal oxide semiconductor technology,”

Ming-Dou Ker and C.-Y. Chang

Japanese Journal of Applied Physics (JJAP) Part 1, vol. 42, no. 6A, pp. 3377-3378, Jun. 2003. (SCI, EI)

“CMOS chip as luminescent sensors for biochemical reactions,”

U. Lu, B. Hu, Y.-C. Shih, Y.-S. Yang, C.-Y. Wu, C.-J. Yuan, Ming-Dou Ker, T.-K. Wu, Y.-K. Li, Y.-Z. Hsieh, W. Hsu, and C.-T. Lin

IEEE Sensors Journal, vol. 3, no. 3, pp. 310-316, Jun. 2003. (SCI, EI)

“Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology,”

Ming-Dou Ker and W.-Y. Lo

IEEE Trans. on Semiconductor Manufacturing, vol. 16, no. 2, pp. 319-334, May 2003. (SCI, EI)

“Substrate-triggered technique for on-chip ESD protection design in a 0.18-µm salicided CMOS process,”

Ming-Dou Ker and T.-Y. Chen

IEEE Trans. on Electron Devices, vol. 50, no. 4, pp. 1050-1057, Apr. 2003. (SCI, EI)

“Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-µm CMOS process,”

Ming-Dou Ker and K.-C. Hsu

IEEE Trans. on Electron Devices, vol. 50, no. 2, pp. 397-405, Feb. 2003. (SCI, EI)

“Substrate-triggered ESD protection circuit without extra process modification,”

Ming-Dou Ker and T.-Y. Chen

IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 295-302, Feb. 2003. (SCI, EI)

“Novel implantation method to improve machine-model electrostatic discharge robustness of stacked NMOS in sub-quarter-micron CMOS technology,”

Ming-Dou Ker, H.-C. Hsu, and J.-J. Peng

Japanese Journal of Applied Physics (JJAP) Part 2, Letters, vol. 41, no. 11B, pp. L1288-L1290, Nov. 2002. (SCI, EI)

“Design and analysis of on-chip ESD protection circuit with very low input capacitance for high-precision analog applications,”

Ming-Dou Ker, T.-Y. Chen, and C.-Y. Wu

International Journal of Analog Integrated Circuits and Signal Processing, Kluwer Academic Pub., vol. 32, pp. 257-278, Sep. 2002. (SCI, EI)

“Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers,”

Ming-Dou Ker and C.-H. Chuang

IEEE Journal of Solid-State Circuits, vol. 37, no. 8, pp. 1046-1055, Aug. 2002. (SCI, EI)

“Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface,”

Ming-Dou Ker and C.-H. Chuang

IEEE Electron Device Letters, vol. 23, pp. 363-365, Jun. 2002. (SCI, EI)

“Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS IC’s,”

Ming-Dou Ker and J.-J. Peng

IEEE Trans. on Components and Packaging Technologies, vol. 25, no.2, pp. 309-316, Jun. 2002. (SCI, EI)

“ESD protection design for CMOS RF integrated circuits using polysilicon diodes,”

Ming-Dou Ker and C.-Y. Chang

Microelectronics Reliability, vol.42, no.6, pp.863-872, Jun. 2002. (SCI, EI)

“Substrate-triggered ESD clamp devices for using in power-rail ESD clamp circuits,”

Ming-Dou Ker, T.-Y. Chen, and C.-Y. Wu

Solid-State Electronics, vol. 46, no. 5, pp. 721-734, May 2002. (SCI, EI)

“Layout design to minimize voltage-dependent variation on input capacitance of an analog ESD protection circuit,”

Ming-Dou Ker and T.-Y. Chen

Journal of Electrostatics, vol. 54, no. 1, pp. 73-93, Jan. 2002. (SCI, EI)

“Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices,”

T.-Y. Chen and Ming-Dou Ker

IEEE Trans. on Device and Materials Reliability, vol. 1, no. 4, pp. 190-203, Dec. 2001.

“Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology,”

Ming-Dou Ker, H.-C. Jiang, and C.-Y. Chang

IEEE Trans. on Electron Devices, vol. 48, no.12, pp. 2953-2956, Dec. 2001. (SCI, EI)

“Hardware/firmware co-design in an 8-bit microcontroller to solve the system-level ESD issue on keyboard,”

Ming-Dou Ker and Y.-Y. Sung

Microelectronics Reliability, vol. 41, no. 3, pp. 417-429, Mar. 2001. (SCI, EI)

“On-chip ESD protection design by using polysilicon diodes in CMOS process,”

Ming-Dou Ker, T.-Y. Chen, T.-H. Wang, and C.-Y. Wu

IEEE Journal of Solid-State Circuits, vol. 36, no. 4, pp. 676-686, Apr. 2001. (SCI, EI)

“ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications,”

Ming-Dou Ker, T.-Y. Chen, C.-Y. Wu, and H.-H. Chang

IEEE Journal of Solid-State Circuits, vol. 35, no. 8, pp. 1194-1199, Aug. 2000. (SCI, EI)

“Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-μm silicide CMOS process,”

Ming-Dou Ker and W.-Y. Lo

IEEE Journal of Solid-State Circuits, vol. 35, no. 4, pp. 601-611, Apr. 2000. (SCI, EI)

“Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger,”

Ming-Dou Ker and H.-H. Chang

Solid-State Electronics, vol. 44, no. 3, pp. 425-445, Mar. 2000. (SCI, EI)

“How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on,”

Ming-Dou Ker and H.-H. Chang

Journal of Electrostatics, vol. 47, no. 4, pp. 215-248, Oct. 1999. (SCI, EI)

“New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness,”

Ming-Dou Ker, T.-Y. Chen, and H.-H. Chang

Microelectronics Reliability, vol. 39, no. 3, pp.415-424, Mar. 1999. (SCI, EI)

“Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology,”

H.-H. Chang, Ming-Dou Ker and J.-C. Wu

Solid-State Electronics, vol. 43, no. 2, pp. 375-393, Feb. 1999. (SCI, EI)

“Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuit for submicron CMOS VLSI,”

Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 46, no.1 , pp. 173-183, Jan. 1999. (SCI, EI)

“ESD protection for slew-rate-controlled output buffer in a 0.5-um CMOS SRAM Technology,”

Ming-Dou Ker and C.-N. Wu

Solid-State Electronics, vol. 42, no.11, pp. 2005-2016, Nov. 1998. (SCI, EI)

“Improved output ESD protection by dynamic gate floating design,”

H.-H. Chang and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 45, no. 9, pp. 2076-2078, Sep. 1998. (SCI, EI)

“Multiple-cell square-type layout design for output transistors in submicron CMOS technology to save silicon area,”

 Ming-Dou Ker, C.-Y. Wu, C.-C. Huang, and T.-Y. Chen

Solid-State Electronics, vol. 42, no. 6, pp. 1007-1014, Jun. 1998. (SCI, EI)

“Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in submicron CMOS technology,”

Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 45, no. 4, pp.849-860, Apr. 1998. (SCI, EI)

“Electrostatic Discharge (ESD) protection for CMOS output buffer in scaled-down CMOS VLSI technology,”

Ming-Dou Ker

Microelectronics Reliability, vol. 38, no. 4, pp.619-639, Apr.1998. (SCI, EI)

“Latchup-free fully-protected input ESD protection circuit for submicron CMOS IC’s,”

Ming-Dou Ker and T.-S. Wu

Solid-State Electronics, vol. 41, no. 9, pp. 1329-1336, Sep. 1997. (SCI, EI)

“ESD protection for CMOS output buffer by using modified LVTSCR devices with high trigger current,”

Ming-Dou Ker

IEEE Journal of Solid-State Circuits, vol. 32, no.8, pp. 1293-1296, Aug. 1997. (SCI, EI)

“Area-efficient layout design for CMOS output transistors,”

Ming-Dou Ker, C.-Y. Wu, and T.-S. Wu

IEEE Trans. on Electron Devices, vol. 44, no. 4, pp. 635-645, Apr. 1997. (SCI, EI)

“ESD protection circuit for output pad with well-coupled field-oxide device in 0.5-μm CMOS technology,”

C.-N. Wu and Ming-Dou Ker

IEEE Trans. on Electron Devices, vol. 44, no. 3, pp. 503-505, Mar. 1997. (SCI, EI)

“A Gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC's,”

Ming-Dou Ker, H.-H. Chang, and C.-Y. Wu

IEEE Journal of Solid-State Circuits, vol. 32, no. 1, pp. 38-51, Jan. 1997. (SCI, EI)

“Efficient output ESD protection for 0.5-μm high-speed CMOS SRAM IC with well-coupled technique,”

Ming-Dou Ker and C.-N. Wu

Microelectronics Reliability, vol. 36, no. 11-12, pp. 1731-1734, Nov.-Dec. 1996. (SCI, EI)

“ESD protection to overcome internal gate-oxide damage on digital-analog interface of mixed-mode CMOS IC's,”

Ming-Dou Ker and T.-L. Yu

Microelectronics Reliability, vol. 36, no. 11-12, pp. 1727-1730, Nov.-Dec. 1996. (SCI, EI)

“Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC,”

Ming-Dou Ker, C.-Y. Wu, T. Cheng, and H.-H. Chang

IEEE Trans. on VLSI Systems, vol. 4, no. 3, pp. 307-321, Sep. 1996. (SCI, EI)

“Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI,”

Ming-Dou Ker, C.-Y. Wu, and H.-H. Chang

IEEE Trans. on Electron Devices, vol. 43, no. 4, pp. 588-598, Apr. 1996. (SCI, EI)

“Complementary-SCR ESD Protection circuit with interdigitated finger-type layout for input pads of submicron CMOS IC’s,”

Ming-Dou Ker and C.-Y. Wu

IEEE Trans. on Electron Devices, vol. 42, no. 7, pp. 1297-1304, Jul. 1995. (SCI, EI)

“Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method : Part I -- theoretical derivation,”

Ming-Dou Ker and C.-Y. Wu

IEEE Trans. on Electron Devices, vol. 42, no. 6, pp. 1141-1148, Jun. 1995. (SCI, EI)

“Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method : Part II -- quantitative evaluation,”

Ming-Dou Ker and C.-Y. Wu

IEEE Trans. on Electron Devices, vol.42, no.6, pp. 1149-1155, Jun. 1995. (SCI, EI)

“Transient analysis of submicron CMOS latchup with a physical criterion,”

Ming-Dou Ker and C.-Y. Wu

Solid-State Electronics, vol. 37, no. 2, pp. 255-273, Feb. 1994. (SCI, EI)

“CMOS on-chip electrostatic discharge protection circuit using four-SCR structures with low ESD-trigger voltage,”

Ming-Dou Ker and C.-Y. Wu

Solid-State Electronics, vol. 37, no. 1, pp. 17-26, Jan. 1994. (SCI, EI)

“A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI,”

C.-Y. Wu, Ming-Dou Ker, C.-Y. Lee, and J. Ko

IEEE Journal of Solid-State Circuits, vol. 27, no. 3, pp. 274-280, Mar. 1992. (SCI, EI)